Fully Molded TSV Interconnect Structure for Compact 3D Packaging
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in producing smaller semiconductor devices with improved electrical interconnects and packaging materials to achieve higher density, efficiency, and reduced form factor.
Innovation Solution
A method involving the use of through silicon vias (TSVs) and a fully molded embedded device with vertical conductive interconnects, where a large semiconductor die is encapsulated and planarized, followed by the formation of build-up interconnect structures to facilitate electrical coupling with other devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional semiconductor manufacturing processes are used, then existing device structures are produced, but the devices cannot achieve smaller form factor and higher density
Solution Approach 1:
The patent transitions from planar 2D interconnect architecture to 3D vertical interconnect architecture using Through-Silicon Vias (TSVs). This dimensional change enables stacking multiple semiconductor dies vertically, achieving higher density and smaller form factor while maintaining manufacturing scalability. The TSV structure allows electrical connections to pass through the substrate thickness, creating vertical pathways that enable three-dimensional device integration.
Solution Approach 2:
The patent implements heterogeneous integration by nesting different types of semiconductor dies (e.g., logic die, memory die, passive device) within a single package structure. Each die type is mounted on or within the substrate and interconnected via TSVs, creating a nested hierarchical arrangement where multiple functional components are integrated in a compact stacked configuration, achieving higher system density.
2Volume of moving object
If device size is reduced, then form factor decreases, but electrical interconnect performance deteriorates
Solution Approach 1:
The patent uses vertical TSV interconnects to replace traditional planar wire bonds and trace routing. This vertical pathway through the substrate reduces the length and complexity of electrical interconnects, improving signal integrity and reducing parasitic effects even as device size decreases. The direct vertical connection minimizes resistance and inductance compared to lateral routing in miniaturized devices.
Solution Approach 2:
The substrate with TSVs acts as an intermediary carrier that provides robust electrical interconnection between stacked semiconductor dies. The TSV structure serves as a mediator that maintains reliable electrical pathways through the substrate thickness, enabling high-performance interconnects while allowing the overall device footprint to be reduced through vertical stacking.
3Reliability
If packaging materials and structures are improved, then electrical connectivity and protection are enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent combines multiple functions into the substrate structure: mechanical support, electrical interconnection (via TSVs), and environmental protection (via encapsulation). The substrate serves as an integrated platform that simultaneously provides structural integrity, vertical electrical pathways, and mounting surfaces for multiple die types, reducing the number of separate components and assembly steps required.
Solution Approach 2:
The patent employs composite packaging structures where the substrate integrates different materials (e.g., silicon, ceramics, or polymer composites) with embedded TSVs. The encapsulant material combines protective properties with electrical insulation, creating a composite structure that provides both mechanical protection and reliable electrical connectivity while being amenable to standardized manufacturing processes.
Data Source
AI summary
A method of making a semiconductor device may include providing a large semiconductor die comprising conductive interconnects with a first encapsulant disposed over four side surfaces of the large semiconductor die, over the active surface of the large semiconductor die, and around the conductive interconnects. A first build-up interconnect structure may be formed over the large semiconductor die and over the first encapsulant. Vertical conductive interconnects may be formed over the first build-up interconnect structure and around an embedded device mount site. An embedded device comprising through silicon vias (TSVs) may be disposed over the embedded device mount site. A second encapsulant may be disposed over the build-up structure, and around at least five sides of the embedded device. A second build-up structure may be formed disposed over the planar surface and configured to be electrically coupled to the TSVs of the embedded device and the vertical conductive interconnects.