Fully Molded TSV Package Stacking Without Solder Interconnects
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in producing smaller, more efficient semiconductor devices with advanced packaging technologies that enable vertical electrical interconnects and package-on-package stacking, while maintaining high performance and reliability.
Innovation Solution
The method involves creating a fully molded semiconductor package with Through Silicon Vias (TSVs) that extend from one surface to the opposite surface, using conductive interconnects and encapsulants to facilitate vertical electrical connections and enable package stacking, without relying on solder interconnects, and forming build-up interconnect structures with conductive RDL layers to directly contact the TSVs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional semiconductor packaging processes are used, then manufacturing simplicity is maintained, but device size reduction and vertical interconnect capability are limited
Solution Approach 1:
The patent embeds the semiconductor die within a molded package structure that contains TSVs, creating a nested configuration where the die is housed inside a protective encapsulant while vertical interconnects pass through the package structure. This nesting enables three-dimensional integration and reduces the overall footprint of the semiconductor device.
Solution Approach 2:
The patent transitions from traditional planar packaging to three-dimensional integration by implementing Through Silicon Vias that extend vertically through the package. This dimensional change enables stackable package-on-package configurations and significantly reduces the lateral footprint while maintaining or increasing functional density.
2Reliability
If solder interconnects are used, then electrical connection is achieved, but manufacturing complexity and reliability risks increase
Solution Approach 1:
The patent removes solder interconnects from the manufacturing process entirely, replacing them with direct wire bonding or conductive adhesive connections. This extraction of the soldering step eliminates associated reliability issues such as solder joint fatigue, thermal expansion mismatches, and manufacturing defects while simplifying the overall manufacturing process.
Solution Approach 2:
The patent employs conductive adhesives or wire bonds that are easier to manufacture and more reliable than solder joints. These alternative interconnect methods eliminate the need for complex solder reflow processes and reduce manufacturing variability, making the process more robust and easier to control.
3Productivity
If package-on-package stacking is implemented, then device density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates alignment features and registration structures during the initial packaging process that facilitate precise stacking of subsequent packages. By preparing the foundation package with built-in alignment mechanisms, the precision requirements for subsequent stacking operations are significantly reduced, enabling higher device density without proportionally increasing manufacturing difficulty.
Solution Approach 2:
The patent uses the molded encapsulant structure as an intermediary that provides mechanical support and alignment references for stacked packages. The encapsulant acts as a buffer and positioning element that accommodates minor variations in package dimensions, reducing the stringency of alignment precision requirements while enabling successful package-on-package integration.
Data Source
AI summary
A semiconductor device may include an embedded device comprising through silicon vias (TSVs) extending from a first surface to a second surface opposite the first surface, wherein the embedded device comprises an active device, a semiconductor die comprising an active surface formed at the first surface, an integrated passive device (IPD), or a passive device. Encapsulant may be disposed over at least five sides of the embedded device. A first electrical interconnect structure may be coupled to a first end of the TSV at the first surface of the embedded device, and a second electrical interconnect structure may be coupled to a second end of the TSV at the second surface of the embedded device. A semiconductor die (e.g. a system on chip (SoC), memory device, microprocessor, graphics processor, or analog device), may be mounted over the first electrical interconnect of the TSV.