Reduced Surface Roughness in Molded Underfill for C-SAM Inspection
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Solution Overview
Problem
Traditional C-SAM methods are unable to detect voids, white bumps, and low-k cracks in semiconductor devices with molded underfill (MUF) packages, especially in low profile packages, limiting quality assurance and increasing semiconductor device failures.
Innovation Solution
A method of forming semiconductor devices with reduced surface roughness in molded underfill by creating a peripheral portion with a first roughness outside the die footprint and a die portion with a second roughness less than the first, allowing for improved acoustic inspection through C-SAM imaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional C-SAM methods are used to inspect molded underfill packages, then the inspection process is simple and cost-effective, but the detection capability for voids, white bumps, and low-k cracks is insufficient
Solution Approach 1:
The patent applies local quality by creating a smooth surface region specifically over the die footprint area, while the peripheral areas maintain their normal roughness. This localized surface treatment enables C-SAM to detect defects in the critical die area without requiring complex inspection process changes elsewhere in the system.
2Measurement precision
If the encapsulant surface is made smooth to improve C-SAM inspection, then defect detection capability is enhanced, but the peripheral areas may be more prone to contamination or handling damage
Solution Approach 1:
The patent implements local quality by differentiating surface roughness between the die footprint area and peripheral areas. The smooth surface over the die footprint enhances C-SAM inspection capability, while the rougher peripheral surfaces maintain their traditional protective characteristics against contamination and handling damage.
Solution Approach 2:
The patent segments the encapsulant surface into two distinct functional zones: a smooth inspection area over the die footprint for optimal C-SAM imaging, and rough peripheral areas for environmental protection. This segmentation allows each zone to optimize its specific function without compromising the other.
3Reliability
If a single roughness level is used for the entire encapsulant surface, then manufacturing is simpler, but C-SAM cannot reliably detect defects in low profile packages
Solution Approach 1:
The patent applies local quality by forming a smooth surface region specifically over the die footprint area using a smooth mold insert, while peripheral areas maintain normal roughness. This localized approach enables reliable defect detection in low profile packages without requiring complex full-surface treatment processes.
4Strength
If polyimide layers are added to the semiconductor device, then flexibility and adhesion are improved, but the surface roughness increases and C-SAM detection capability deteriorates
Solution Approach 1:
The patent applies local quality by creating a smooth surface region over the die footprint area that extends through the polyimide layers. This localized smooth region, formed using a smooth mold insert during encapsulation, maintains the adhesion benefits of polyimide while enabling C-SAM to detect defects through the reduced roughness area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reliable detection of voids and cracks in low profile MUF packages, enhancing quality assurance and reducing semiconductor device failures by producing clearer C-SAM images that can identify defects as small as 95-100 μm in diameter, even with PI layers present.
Implementation Method 1
C-Mode Scanning Acoustic Microscope (C-SAM) inspection
Data Source
AI summary
A semiconductor device includes a semiconductor die. An interconnect structure is formed over an active surface of the semiconductor die. An encapsulant is formed over the semiconductor die and interconnect structure including a first surface opposite the interconnect structure. A peripheral portion of the first surface includes a first roughness disposed outside a footprint of the semiconductor die. A semiconductor die portion of the first surface includes a second roughness less than the first roughness disposed over the footprint of the semiconductor die. The first surface of the encapsulant is disposed within a mold and around the semiconductor die to contact a surface of the mold that includes a third roughness equal to the first roughness and a fourth roughness equal to the second roughness. The first roughness includes a roughness of less than 1.0 micrometers. The second roughness includes a roughness in a range of 1.2-1.8 micrometers.