Molding Guide Pattern Layout for Void-Resistant Semiconductor Packages
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving improved performance, reliability, and reduced defects, particularly due to issues related to the molding process that can lead to voids and damage under thermal stress.
Innovation Solution
The semiconductor package design incorporates a package substrate with lower and upper molding guide patterns and dams, along with a molding layer that covers the semiconductor chip and extends between the package substrate and the chip, effectively restricting the flow of the molding material and preventing void formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional molding process is used without guide patterns, then manufacturing simplicity is maintained, but void formation and defects occur under thermal stress
Solution Approach 1:
The molding guide pattern is divided into multiple segments including lower molding guide patterns, upper molding guide dams, and first/second portions. This segmentation allows the molding material to flow in a controlled manner through defined paths, preventing void formation while maintaining manufacturing feasibility through modular pattern design
Solution Approach 2:
The molding guide patterns and dams are formed in advance on the package substrate before the molding process. These pre-formed structures create predetermined flow paths that guide the molding material during injection, ensuring complete filling and preventing voids before the actual molding occurs
2Manufacturing precision
If molding material flows freely during molding process, then complete coverage is achieved, but voids form under the chip
Solution Approach 1:
The molding guide pattern provides different functions at different locations: the lower molding guide patterns (first portion) constrain material flow near the substrate, while the upper molding guide dams (second portion) control flow near the chip. This localized quality control ensures proper material distribution without requiring complex overall process changes
Solution Approach 2:
The molding guide patterns act as intermediary structures between the molding material and the chip/substrate assembly. These patterns mediate the material flow by providing defined paths and constraints, ensuring the material reaches all necessary areas without forming voids, while keeping the manufacturing process relatively simple
3Strength
If molding layer is applied to cover chip sidewalls, then mechanical protection is improved, but material flow control becomes difficult
Solution Approach 1:
The molding guide structures extend in the vertical dimension with lower patterns on the substrate plane and upper dams rising to constrain material flow. This multi-dimensional arrangement provides both horizontal flow guidance and vertical confinement, ensuring the molding material properly covers chip sidewalls while maintaining precise flow control throughout the molding process
Data Source
AI summary
A semiconductor package includes a package substrate, a lower molding guide pattern disposed over the package substrate and including a first portion and a second portion, a semiconductor chip disposed over an upper surface of the package substrate and over an upper surface of the first portion of the lower molding guide pattern, an upper molding guide dam over the second portion of the lower molding guide pattern, and a molding layer covering a side surface of the semiconductor chip and extending between the package substrate and a lower surface of the semiconductor chip, wherein the upper molding guide dam is disposed laterally with respect to the semiconductor chip.