Molecular Clock Calibration Using Dual Divisor Frequency Control
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Solution Overview
Problem
Molecular clocks face challenges in correcting drift, error signals, and noise in the signal channel due to limitations in calibration within the closed loop, which affects the stability and accuracy of the frequency reference.
Innovation Solution
An electronic device with a controller that provides divisor values to regulate a closed loop including a physics cell, receiver, and phase-locked-loop (PLL), allowing for external calibration and compensation of frequency drifts and noise through separate control of the output clock circuit, enabling precise frequency maintenance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If calibration is performed within the closed loop, then frequency accuracy is improved, but drift, error signals and noise in the signal channel cannot be corrected
Solution Approach 1:
The system divides frequency control into two independent segments: a closed-loop PLL for fast frequency locking and an external clock circuit for long-term stability. The PLL handles short-term frequency corrections while the external clock circuit, calibrated separately, provides drift compensation over time. This segmentation allows each subsystem to optimize for its specific function without interfering with the other.
Solution Approach 2:
A divisor circuit acts as an intermediary between the PLL and the external clock circuit. This mediator receives frequency signals from both sources and combines them appropriately, allowing the system to benefit from both the fast response of the PLL and the long-term stability of the external clock while preventing direct interference between the two control loops.
2Stability of the object's composition
If the closed loop corrects frequency errors, then short-term stability is improved, but long-term drift and noise cannot be compensated
Solution Approach 1:
The external clock circuit is calibrated in advance using a known reference frequency before being used to compensate for long-term drift. This preliminary calibration establishes accurate divisor values that account for systematic errors and drift characteristics. The pre-calibrated external clock then operates independently to provide continuous long-term frequency correction without requiring continuous feedback.
3Device complexity
If a single clock circuit is used, then device complexity is reduced, but the ability to correct both short-term and long-term errors is insufficient
Solution Approach 1:
The system merges two clock circuits (PLL and external clock) with different strengths into a unified frequency output. The PLL provides fast locking and short-term stability while the external clock provides long-term drift compensation. A divisor circuit combines their outputs, creating a composite frequency signal that benefits from both sources without requiring complex switching or selection logic.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables ultra-stable frequency output with sub-parts per billion accuracy by effectively addressing temperature, aging, and other error sources, maintaining frequency stability despite internal drifts and noise.
Implementation Method 1
A first divisor value is provided to a control input of a phase-locked-loop (PLL) to regulate a closed loop that includes a physics cell, a receiver, and the PLL
Implementation Method 2
Molecular or atomic clocks include a signal channel with a transmitter, a physics cell, and a receiver
Data Source
AI summary
A method, providing an oscillator output signal to reference inputs of a PLL and an output clock circuit; providing a first divisor value to a control input of the PLL to regulate a closed loop that includes a physics cell, a receiver, and the PLL; providing a second divisor value to a control input of the output clock circuit to control an output frequency of an output clock signal; shifting the first divisor value in a first direction to cause a perturbation in the closed loop; shifting the second divisor value in an opposite second direction to counteract a response of the closed loop to the perturbation and to regulate the output frequency of the output clock signal; and based on the receiver output signal, analyzing the response of the closed loop to the perturbation.