Molecular Synthesis Device Electrode Control via Non-Volatile Memory
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Solution Overview
Problem
Large-scale molecular synthesis arrays face challenges in efficiently controlling electrodes due to the impracticality of providing dedicated supply lines for each electrode, especially in arrays with billions of memory cells, which hinders the development of reliable and cost-effective molecular memories.
Innovation Solution
The solution involves connecting each electrode in the synthesis array to the first source/drain terminal of a non-volatile memory transistor, allowing for individual control through a pattern stored in the bit cells of the non-volatile memory, enabling parallel activation of synthesis reactions and reducing the need for dedicated control lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a dedicated supply line is provided to each electrode in a large-scale synthesis array, then individual control of electrodes is achieved, but the device complexity and manufacturing impracticality increase significantly
Solution Approach 1:
The patent merges the electrode control function with the existing non-volatile memory bit cell structure. Each memory transistor's first source/drain terminal is repurposed to serve as an electrode, combining storage and synthesis control functions into a single integrated structure, thereby eliminating the need for separate supply lines to each electrode.
Solution Approach 2:
The memory transistor serves multiple functions: it stores data in the bit cell and simultaneously acts as a controllable electrode for the synthesis reaction. This multi-functionality allows the same structure to perform both memory and actuation roles, reducing the overall number of components and connections required.
2Ease of operation
If a dedicated supply line is provided to each electrode, then selective activation is enabled, but the manufacturing cost and practicality deteriorate for arrays with billions of cells
Solution Approach 1:
The control signal path is merged with the memory read-out path. The bit line that reads memory data is reused to supply control signals to the electrodes, and the word line structure enables selective activation patterns. This eliminates the need for separate control wiring infrastructure, making manufacturing scalable to billions of cells.
Solution Approach 2:
The memory transistor's inherent structure provides the control mechanism. The transistor's switching behavior, controlled by standard memory control signals, automatically enables selective electrode activation without requiring additional control circuitry or complex wiring, allowing the structure to serve itself for both storage and actuation.
3Device complexity
If serial/sequential activation of electrodes is used, then the control infrastructure is simplified, but the productivity and data throughput decrease significantly
Solution Approach 1:
The system dynamically switches between different activation patterns by controlling which word lines are active. This allows the same hardware infrastructure to support both simple sequential operation and complex parallel operation, optimizing productivity without increasing infrastructure complexity. The dynamic control is achieved through standard memory control signals.
Solution Approach 2:
The bit lines and word lines serve dual purposes: they control the synthesis reactions (acting as electrodes) and simultaneously enable parallel operation across multiple memory locations. This multi-functionality allows the same control infrastructure to support both sequential and parallel operation modes, achieving high productivity without additional complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient and parallel control of chemical synthesis reactions across millions or billions of synthesis locations, improving the feasibility and scalability of molecular memories by allowing simultaneous activation of electrodes, thus enhancing data storage capabilities.
Implementation Method 1
Each bit cell comprises a non-volatile memory transistor having a control gate connected to a wordline, a first source/drain terminal, and a second source/drain terminal connected to a bitline. The memory transistor is switchable between a low threshold voltage and a high threshold voltage.
Implementation Method 2
The electrodes may, for instance, supply thermal energy, generate bubbles or generate ions in the synthesis compartment, to enable the chemical reaction.
Implementation Method 3
The electrodes may, for instance, supply thermal energy, generate bubbles or generate ions in the synthesis compartment, to enable the chemical reaction.
Implementation Method 4
stable organic molecules (such as polymers, DNA or RNA) are synthesized in a structured manner to form molecules mapping to data symbols. Being aware of the data encoding scheme employed during writing, i.e. the mapping between data symbols and the building structures of the synthesized molecules, the written data symbols may, accordingly, be read-out from the structure of the synthesized molecules, e.g. the sequence of monomers (for polymers) or base pairs (for DNA or RNA).
Data Source
AI summary
The disclosed technology relates to a molecular synthesis device. In one aspect, the molecular synthesis device comprises a synthesis array having an array of synthesis locations and an electrode arranged at each synthesis locations. The molecular synthesis device further comprises a non-volatile memory having an array of bit cells and a set of wordlines and a set of bitlines. Each bit cell comprises a non-volatile memory transistor having a control gate connected to a wordline, a first source/drain terminal, and a second source/drain terminal connected to a bitline. The electrode at each synthesis locations of the synthesis array is connected to the first source/drain terminal of a corresponding bit cell of the non-volatile memory.