3D Memory Block Structure With Molybdenum Edges for Wordline Access
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Solution Overview
Problem
Existing methods for forming memory arrays face challenges in efficiently connecting memory cells and ensuring reliable electrical coupling, particularly in vertically-stacked structures like NAND architecture, where stair-step structures complicate access to wordlines.
Innovation Solution
The method involves forming memory blocks with alternating insulative and conductive tiers, using conductive molybdenum-containing metal material at the edges, and extending channel-material strings through these tiers, with additional silicon nitride and insulator layers to enhance electrical connectivity and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically-stacked memory structures are used to increase storage density, then the storage capacity is improved, but the complexity of electrical access and structural fabrication increases
Solution Approach 1:
The memory array is divided into multiple memory blocks, each containing vertically-stacked memory cells organized into distinct tiers. Each tier has dedicated wordline structures, allowing independent access to different segments of the vertical stack. This segmentation enables complex storage density while managing electrical access complexity through modular organization.
Solution Approach 2:
The patent transitions from planar memory architecture to three-dimensional vertically-stacked architecture. Memory cells are arranged in vertical columns extending through multiple tiers, with wordlines wrapping around or extending along the vertical dimension. This dimensional change dramatically increases storage capacity per unit area while requiring new approaches to electrical access.
2Ease of operation
If stair-step structures are used to provide wordline access in vertically-stacked memory, then electrical access to individual wordlines is enabled, but the structural complexity and manufacturing difficulty increase
Solution Approach 1:
Wordline structures are nested within and around the vertical memory cell stacks. Conductive materials are positioned at different elevations and lateral positions, with some wordlines embedded within the stack and others extending outward. This nested arrangement enables access to multiple wordlines while reducing the need for complex external routing structures.
Solution Approach 2:
Conductive vias and intermediate connection structures serve as mediators between the vertically-stacked memory cells and external access points. These intermediary elements facilitate electrical coupling between different tiers and wordlines, simplifying the overall access structure while enabling independent control of each wordline tier.
3Reliability
If additional conductive and insulative tiers are added to enhance electrical connectivity, then the electrical coupling is improved, but the manufacturing process complexity increases
Solution Approach 1:
Alternating conductive and insulative tiers are formed during the initial fabrication sequence before final memory cell assembly. This preliminary formation of the tiered structure establishes the electrical connectivity framework early in the manufacturing process, enabling subsequent steps to build upon this pre-configured architecture and reducing overall process complexity.
Solution Approach 2:
The patent employs composite structures combining conductive materials (such as doped polysilicon or metal) with insulative materials (such as oxide or nitride layers) in alternating tiers. This composite arrangement provides both electrical connectivity through conductive paths and electrical isolation through insulative barriers, achieving reliable electrical coupling while maintaining manufacturability through standard semiconductor fabrication techniques.
Data Source
AI summary
A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Individual of the conductive tiers comprise laterally-outer edges comprising conductive molybdenum-containing metal material extending horizontally-along its memory block. Channel-material strings extend through the insulative tiers and the conductive tiers. At least one of conductive or semiconductive material is formed extending horizontally-along the memory blocks laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material that extends horizontally-along its memory block. Insulator material extending horizontally-along the memory blocks is formed laterally-outward of the at least one of the conductive or the semiconductive material that is laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material. Other embodiments, including structure independent of method, are disclosed.