Molybdenum-Lined Tungsten Interconnects for Sub-15 Nm Scaling
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Solution Overview
Problem
Current integrated circuit fabrication processes face challenges in scaling to sub-15 nanometer nodes due to variability in conventional methods, particularly in achieving precise overlay and critical dimension control for vias and metal lines, which limits the extension of technology nodes and requires new methodologies or technologies.
Innovation Solution
The use of a molybdenum liner with a tungsten fill, deposited using conformal physical vapor deposition or atomic layer deposition, addresses issues of adhesion, fluorine barrier, and delamination, enabling conformal growth and resistive-linerless fill for high aspect ratio features, and the implementation of hybrid metal layers with Co or Ru for initial metallization followed by tungsten with a molybdenum barrier for optimized performance across different line widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at sub-15 nanometer nodes
Solution Approach 1:
The fabrication process is divided into multiple specialized stages: forming mandrels, depositing first spacers for pitch quartering, selective removal, depositing second spacers, and final trench formation. This segmentation allows each stage to be optimized independently for precision while managing overall process complexity.
Solution Approach 2:
Mandrels and spacer structures are formed in advance before the final trench etching. The spacers are deposited and patterned preliminarily to define the precise locations and dimensions of the trenches, ensuring critical dimension control before the actual conductive line formation.
2Manufacturing precision
If feature size is reduced to increase density, then capacity increases, but variability in fabrication processes worsens
Solution Approach 1:
The spacer structures self-align to the mandrels through conformal deposition, automatically defining precise pitch relationships without requiring additional alignment steps. This self-service mechanism reduces variability by eliminating manual overlay adjustments and ensuring consistent critical dimensions.
Solution Approach 2:
The process transforms the critical dimension control problem from direct lithographic patterning to spacer thickness control. By changing the controlling parameter from lithographic resolution to deposition thickness (which can be controlled more precisely), manufacturing precision is improved while reducing the impact of process variability.
3Manufacturing precision
If new methodologies are introduced to extend technology nodes, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The spacer-based pitch quartering methodology serves multiple functions: it defines trench locations, controls trench pitch, ensures alignment, and creates self-aligned structures. This multi-functionality reduces the need for separate process steps, managing device complexity while maintaining improved manufacturing precision.
Solution Approach 2:
The spacers act as intermediary structures that mediate between the lithographically-defined mandrels and the final trench patterns. These intermediaries enable precise pitch quartering and alignment without requiring direct lithographic patterning at the final critical dimensions, thus improving precision while managing process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved performance with reduced feature resistance by 30-50%, allowing for faster CPU or server chip performance without the need for a molybdenum slurry, easing integration, and enabling rapid polish development and drop-in integration, while maintaining low electromigration and resistivity.
Implementation Method 1
deposited using conformal physical vapor deposition or atomic layer deposition
Implementation Method 2
deposited using conformal physical vapor deposition or atomic layer deposition
Data Source
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AI summary
Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive lines, individual ones of the plurality of conductive lines having a liner including molybdenum (Mo), and a fill including tungsten (W). The integrated circuit structure also includes an inter-layer dielectric (ILD) structure having portions between adjacent ones of the plurality of conductive lines.