3D Interdigitated MOM Capacitor for High Density IC Design
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Solution Overview
Problem
Pre-existing Metal-Oxide-Metal (MOM) capacitors in integrated-circuit devices do not provide sufficient capacitance per unit area, limiting their effectiveness in semiconductor integrated circuitry.
Innovation Solution
A semiconductor device with a capacitor structure featuring interdigitated comb electrodes in multiple layers, where each layer's finger wirings are connected through vias to maximize capacitance per unit area, forming a compact capacitor structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional MOM capacitor structures are used, then the device complexity is low and ease of manufacture is good, but the capacitance per unit area is insufficient
Solution Approach 1:
The patent transitions from planar 2D capacitor layouts to a 3D stacked architecture utilizing multiple wiring layers (first, second, and third wiring layers with comb electrodes and unit electrodes). This vertical dimensionality multiplication dramatically increases the effective capacitance area within the same chip footprint, directly resolving the contradiction between capacitance density and structural complexity.
Solution Approach 2:
The capacitor structure implements nested electrode arrangements where comb electrodes and unit electrodes are interdigitated across multiple layers. The first comb electrodes, second comb electrodes, and unit electrodes are positioned to overlap and interleave, creating a nested configuration that maximizes capacitance per unit area by utilizing space efficiently in the vertical stacking direction.
2Quantity of substance
If capacitor area is increased to achieve required capacitance, then the capacitance per unit area improves, but the area occupied on the chip increases
Solution Approach 1:
The patent resolves this area-capacitance tradeoff by stacking capacitor elements vertically across multiple wiring layers instead of expanding horizontally. The first comb electrodes, second comb electrodes, and unit electrodes are distributed across at least three different wiring layers, enabling the accumulation of total capacitance in the vertical dimension while maintaining a compact chip footprint.
Solution Approach 2:
The capacitor is segmented into multiple discrete electrode pairs distributed across different wiring layers. Each layer contains comb electrodes and unit electrodes that form individual capacitance contributions, which are then combined to achieve the required total capacitance. This segmentation allows the total capacitance to be distributed across multiple small areas rather than requiring one large continuous area.
3Quantity of substance
If more wiring layers are used to increase capacitance, then the capacitance per unit area improves, but the manufacturing process complexity increases
Solution Approach 1:
The patent employs existing standard wiring layers and via structures from the semiconductor fabrication process to implement the capacitor. The first comb electrodes, second comb electrodes, and unit electrodes are formed using the same material deposition and patterning techniques as the surrounding circuit interconnect, allowing the capacitor structure to be integrated into the standard manufacturing flow without requiring entirely new process equipment or techniques.
Solution Approach 2:
The capacitor manufacturing process is merged with the standard semiconductor fabrication process. The electrode patterns are formed using the same lithography, etching, and metallization steps that create the surrounding circuitry. Vias connecting the electrodes across layers utilize the same via formation and filling processes, thereby combining capacitor fabrication with general IC manufacturing and avoiding separate specialized processing steps.
Data Source
Figure 1A
Figure 1B
Figure 2(a)~2(c)
AI summary
An integrated-circuit device having a layered structure, the layered structure comprising a plurality of wiring layers with a via layer sandwiched between adjacent said wiring layers, wherein: a capacitor having first and second terminals is formed from conductive structures implemented in at least first and second said wiring layers, the conductive structures comprising arrangements of conductive strips; the strips formed in the first wiring layer are organised into at least a first-terminal comb arrangement conductively connected to the first terminal and a second-terminal comb arrangement conductively connected to the second terminal, each of those comb arrangements having a base strip and a plurality of finger strips extending from the base strip; and the strips formed in the second wiring layer comprise a plurality of separate strips which constitute finger strips of a cross-layer comb arrangement whose base strip is a finger strip of the first-terminal comb arrangement of the first wiring layer to which those separate strips are conductively connected by vias.