Ultra High Density Metal-Oxide-Metal Capacitor With 3D Vertical Stacking
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Solution Overview
Problem
MOM capacitors in integrated circuits, including FinFETs, face challenges in achieving high capacitance without increasing silicon area, which leads to higher costs and reduced density due to the use of low-k materials that result in lower capacitance and susceptibility to low breakdown voltage.
Innovation Solution
The implementation of a structure with multiple metallization layers, multiple oxide dielectric layers, and a metallization diffusion (MD) layer within a shallow trench isolation (STI) structure, where the MD layer is formed with high density conductive traces, increasing capacitance without requiring additional mask or process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If larger silicon area is used to achieve higher capacitance, then capacitance increases, but IC cost increases and FinFET density decreases
Solution Approach 1:
The patent transitions from planar 2D capacitor structures to 3D vertical structures by forming metal plates and oxide dielectric layers in multiple stacked layers. The capacitor extends vertically through the substrate with metal plates at different depths, utilizing the third dimension (depth) to increase capacitance without expanding the horizontal silicon footprint.
Solution Approach 2:
The capacitor structure is nested within the substrate by forming metal plates and oxide dielectric layers that extend into and between substrate regions. The capacitor structure is embedded or nested within the existing IC architecture, with metal plates positioned at different vertical levels and connected through conductive vias, effectively nesting the capacitor within the substrate volume.
2Object-generated harmful factors
If low-k materials are used in MOM capacitors, then parasitic capacitance is reduced, but breakdown voltage decreases and capacitance is reduced
Solution Approach 1:
The patent applies different dielectric materials with different k-values in different spatial locations and layers. High-k materials are used in specific oxide dielectric layers where capacitance enhancement is needed, while low-k materials may be used in other regions for parasitic capacitance reduction. This localized material selection allows optimization of both capacitance and breakdown voltage in different parts of the capacitor structure.
Solution Approach 2:
The capacitor structure employs composite dielectric systems combining multiple oxide materials with different electrical properties. By stacking oxide dielectric layers with different k-values and breakdown characteristics, the structure achieves a balance between parasitic capacitance reduction and maintained breakdown voltage, with each layer contributing different functional properties to the overall capacitor performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances capacitance while maintaining a compact design, reducing the need for extra resources and maintaining high breakdown voltage, thus addressing the limitations of low-k materials in MOM capacitors.
Implementation Method 1
A MOM capacitor structure is disclosed including a first terminal connector, a second terminal connector, multiple metallization layers including an M0 layer, a metallization diffusion (MD) layer formed below the M0 layer, and multiple oxide dielectric layers including a first oxide dielectric layer situated between the M0 layer and the MD layer
Data Source
AI summary
A capacitor includes a shallow trench isolation (STI) layer disposed on top of a substrate. The capacitor also includes a first dielectric layer disposed on top of the STI layer. The capacitor further includes a metallization diffusion (MD) layer disposed within both of the STI layer and the first dielectric layer.