MOM Capacitor Arrays for Interconnect Misalignment Detection
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Solution Overview
Problem
Existing methods for monitoring interconnect fabrication processes in integrated circuits are inadequate, failing to effectively detect misalignments, low-k dielectric material damage, and voids between metal lines, which can lead to yield loss and reliability issues.
Innovation Solution
The use of metal-oxide-metal (MOM) capacitors to monitor interconnect process quality by detecting misalignments, low-k dielectric material damage, and voids through electrical testing and analysis of capacitance and breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional monitoring structures (metal comb structures, serpentine metal structures, chain-like structures) are used to detect interconnect defects, then simple fabrication and basic defect detection are achieved, but detection precision for misalignments, low-k dielectric material damage, and voids is insufficient
Solution Approach 1:
The monitoring structure is segmented into multiple functional components: MOM capacitor structures for electrical parameter measurement, low-k dielectric material regions for damage detection, and via structures for alignment detection. Each segment serves a specific detection function, enabling comprehensive monitoring of multiple interconnect parameters simultaneously.
Solution Approach 2:
The monitoring structure integrates multiple detection capabilities into a single unified structure that can simultaneously detect via-to-metal misalignment, low-k dielectric material damage, and voids between metal lines. This multi-functional approach eliminates the need for separate monitoring structures for each defect type.
2Reliability
If existing monitoring techniques are used, then basic electrical resistance measurement is achieved, but the ability to detect process-related misalignments and material damage is inadequate
Solution Approach 1:
MOM capacitor structures serve as intermediary elements that translate physical defects (misalignment, damage, voids) into measurable electrical parameter changes. The capacitors are positioned to sense mechanical and material variations in the interconnect structure, converting these physical states into electrical signals for detection.
Solution Approach 2:
The monitoring method detects defects by measuring changes in electrical parameters (capacitance, resistance, breakdown voltage) of the MOM capacitors. These parameter changes correlate with physical defects in the interconnect structure, enabling indirect detection of misalignment, damage, and voids through electrical characterization.
3Adaptability or versatility
If simple monitoring structures are used, then fabrication ease is maintained, but the ability to monitor multiple interconnect parameters simultaneously is lost
Solution Approach 1:
Multiple monitoring functions are merged into a single integrated structure containing MOM capacitors, low-k dielectric regions, and via structures. This combined structure can monitor via-to-metal alignment, dielectric material integrity, and void formation simultaneously, providing comprehensive interconnect quality assessment in one fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
MOM capacitors enable accurate detection and analysis of process-related misalignments and material damage, allowing for corrective actions to improve interconnect quality and reliability.
Implementation Method 1
metal-oxide-metal (MOM) capacitors to monitor interconnect process quality by detecting misalignments, low-k dielectric material damage, and voids through electrical testing and analysis of capacitance and breakdown voltage
Implementation Method 2
electrical testing and analysis of capacitance and breakdown voltage
Data Source
AI summary
An array of metal-oxide-metal (MOM) capacitors formed in an integrated circuit (IC) structure may be used for evaluating misalignments between patterned layers of the IC structure. The array of MOM capacitors may be formed in a selected set of patterned layers, e.g., a via layer formed between a pair of metal interconnect layers. The MOM capacitors may be programmed with different patterned layer alignments (e.g., built in to photomasks or reticles used to form the patterned layers) to define an array of different alignments. When the MOM capacitors are formed on the wafer, the actual patterned layer alignments capacitors may differ from the programmed layer alignments due a process-related misalignment. The MOM capacitors may be subjected to electrical testing to identify this process-related misalignment, which may be used for initiating a correcting action, e.g., adjusting a manufacturing process or discarding misaligned IC structures or devices.