MoN Gate-All-Around Nanowire Gates With Dipole Threshold Tuning
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Solution Overview
Problem
The scaling of multi-gate and nanowire transistors in integrated circuits faces challenges such as maintaining mobility and short channel control as dimensions approach the 10 nanometer node, with conventional lithographic processes facing constraints in pattern dimension and spacing, and existing metal gate processes involving halide-based precursors that can poison devices.
Innovation Solution
The use of molybdenum nitride (MoN) liners deposited with metal-organic precursors for atomic layer deposition, allowing for two-operation filling of gates with tungsten, and the implementation of additive metal gate flows to bypass isotropic wet etch removal issues, along with the incorporation of dipole layers to tune threshold voltage and reduce workfunction metal thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional lithographic processes are used to pattern features, then existing manufacturing capabilities are maintained, but the smallest feature dimension and spacing between features cannot be sufficiently reduced
Solution Approach 1:
The patent transitions from planar 2D patterning to 3D vertical structures by forming nanowires and gate-all-around configurations. This dimensional change allows continued scaling of effective channel length without proportionally reducing lithographic feature sizes, as the gate controls the channel from all directions including sidewalls.
Solution Approach 2:
The gate structure is segmented into multiple components: a bottom gate portion formed in a trench, and sidewall gate portions formed on the nanowire sidewalls. This segmentation allows independent optimization of each gate portion and enables better electrostatic control without requiring proportional reduction in lithographic dimensions.
2Ease of manufacture
If halide-based precursors are used in metal gate processes, then metal gates can be formed, but device poisoning and contamination occur
Solution Approach 1:
The patent changes the chemical composition parameters of the precursor materials from halide-based to non-halide-based formulations. This parameter change maintains the ability to form metal gates through ALD while eliminating the harmful halogen byproducts that cause device poisoning and contamination.
Solution Approach 2:
The patent converts the previously harmful halide-based chemistry into a beneficial non-halide chemistry that eliminates contamination issues. The new precursor formulation maintains effective metal gate formation while the absence of halogen elements prevents device poisoning, effectively converting a harmful process into a clean process.
3Productivity
If gate length is aggressively scaled down, then transistor density increases, but short channel control deteriorates
Solution Approach 1:
The gate-all-around structure extends gate control into the vertical dimension by wrapping the gate around the nanowire channel. This provides electrostatic control from the bottom, top, and sidewalls simultaneously, maintaining effective short channel control even when the horizontal gate length is aggressively scaled down to increase density.
Solution Approach 2:
The gate structure uses composite materials including a high-k dielectric layer and a metal gate layer. The high-k dielectric provides enhanced electric field control with thinner physical thickness, while the metal gate provides optimal work function and conductivity, together maintaining reliable short channel control at scaled dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces defect susceptibility and cost while maintaining high transistor density and performance, enabling aggressive gate length scaling with improved short channel control and reduced contamination risks.
Implementation Method 1
molybdenum nitride (MoN) liners deposited with metal-organic precursors for atomic layer deposition
Implementation Method 2
incorporation of dipole layers to tune threshold voltage and reduce workfunction metal thickness
Data Source
AI summary
Gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer on a first gate dielectric. The P-type conductive layer includes molybdenum and nitrogen. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer on a second gate dielectric.