Monarchy Core Exception Handling for Storage Class Memory

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Solution Overview

Problem

Conventional memory systems face performance limitations in controlling storage class memory due to its characteristics, which hinder efficient error handling and system stability, particularly when accessing nonvolatile memory modules.

Innovation Solution

A memory system architecture that includes a processor with cores and a memory controller, where a monarchy core handles exceptions for errors detected during data access from nonvolatile memory modules, while other cores return to previous operations, ensuring efficient error management and system stability without kernel panics or reboots.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional error handling methods are used for storage class memory, then system stability is maintained, but performance deteriorates due to kernel panics and reboots

Engineering Contradiction:
Improvesystem stabilityVSAvoidmemory access performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The error handling process is segmented by assigning a dedicated monarchy core specifically for exception handling, separating this function from the execution cores. This segmentation allows error handling to proceed independently without affecting the performance of other memory operations, thus maintaining system stability while preserving memory access performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The monarchy core acts as an intermediary between the memory controller and the execution cores for exception handling. It receives error signals from the memory controller and manages the exception handling process, preventing direct interference with memory access operations and avoiding kernel panics that would cause reboots.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If all cores perform exception handling, then error handling completeness is improved, but system performance decreases due to resource wastage

Engineering Contradiction:
Improveerror handling completenessVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The processor cores are segmented into a monarchy core dedicated to exception handling and execution cores responsible for memory operations. This segmentation ensures that error handling is performed completely by the monarchy core while execution cores continue their operations without resource wastage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The exception handling function is extracted from the execution cores and assigned to a dedicated monarchy core. This extraction allows error handling to be performed thoroughly without requiring execution cores to divert resources, thus maintaining system performance while ensuring error handling completeness.

Inventive Principle:
Principle #2Taking out (Extraction)

3Quantity of substance

If storage class memory is used as main memory, then capacity is increased, but error handling performance deteriorates

Engineering Contradiction:
Improvememory capacityVSAvoiderror handling performance
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The processor architecture is segmented with a dedicated monarchy core for error handling, allowing efficient error handling performance even when storage class memory provides large capacity. The segmentation ensures that error handling operations do not interfere with the high-capacity memory operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The monarchy core serves as an intermediary that efficiently handles errors from storage class memory without affecting the high-capacity memory operations. It mediates between the memory controller and execution cores, ensuring rapid error handling that does not degrade the performance benefits of using storage class memory as main memory.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11157342B2Memory systems and operating methods of memory systems
Publication Date: 2021.10.26 SAMSUNG ELECTRONICS CO LTD
  • US11157342B2 patent drawing
  • US11157342B2 patent drawing
  • US11157342B2 patent drawing

AI summary

A memory system includes a processor that includes cores and a memory controller, and a first semiconductor memory module that communicates with the memory controller. The cores receive a call to perform a first exception handling in response to detection of a first error when the memory controller reads first data from the first semiconductor memory module. A first monarchy core of the cores performs the first exception handling and the remaining cores of the cores return to remaining operations previously performed.