Monitor Circuit for DMA Bus Cycle Address Matching
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Solution Overview
Problem
In computer systems, the CPU may access memory regions before DMA write operations are complete, leading to the CPU reading old data instead of new data, due to increased processing speeds outpacing data transfer speeds, especially in hierarchical bus structures with buffers.
Innovation Solution
A monitor circuit is introduced to monitor addresses on the bus and control CPU access, ensuring that the CPU only accesses memory after confirming the completion of DMA write operations by comparing target addresses with acquisition addresses and providing access permission only when they match.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the CPU processing speed is increased, then the CPU execution speed is improved, but the CPU may access memory before DMA write operations are complete, causing data integrity issues
Solution Approach 1:
A monitor circuit is introduced as an intermediary component between the CPU and memory. This monitor circuit observes DMA bus cycles and controls CPU access to memory based on DMA completion status, preventing the CPU from reading data before DMA write operations are complete while allowing the CPU to maintain high processing speed
Solution Approach 2:
The monitor circuit implements a feedback mechanism by continuously monitoring DMA bus cycles and using this information to control CPU memory access. When the monitor detects that a DMA write operation is complete, it allows CPU access; otherwise, it prevents access, ensuring data integrity while maintaining CPU efficiency
2Reliability
If a monitor circuit is introduced to control CPU access based on DMA completion, then data integrity is improved, but the system complexity increases
Solution Approach 1:
The monitor circuit serves as a dedicated intermediary component that handles the complexity of coordinating between CPU and DMA operations. By isolating this control logic in a separate monitor circuit rather than integrating it into the CPU or DMA controller, the system maintains modularity and manages complexity effectively while ensuring data integrity
3Measurement precision
If the CPU waits for DMA completion before accessing memory, then data accuracy is improved, but the CPU productivity decreases
Solution Approach 1:
The system dynamically controls CPU access to memory based on real-time DMA operation status. The monitor circuit enables the CPU to access memory when DMA operations are complete while preventing access during active DMA writes. This dynamic control allows the CPU to maintain high productivity by avoiding unnecessary waits while ensuring data accuracy when access is permitted
Data Source
AI summary
A data processing apparatus contains a first bus connected to a first memory, a first central processing unit (CPU) being accessible to the first memory via the first bus, a first Direct Memory Access (DMA) controller being accessible to the first memory via the first bus, and a monitor circuit connected to the first bus and monitoring addresses transferred on the first bus. The addresses transferred on the first bus are transmitted from the first DMA controller to the first memory via the first bus. The monitor circuit compares the address transferred on the first bus with a preset monitor target address. The CPU acquires the comparison results by the monitor circuit. If the comparison results show an address match, then the CPU accesses the first memory. The CPU can in this way access the first memory at a correct timing.