Monitor Structures for Impedance Measurement in Scribe Lines
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Solution Overview
Problem
Existing impedance measurement techniques for semiconductor wafers lack accuracy due to the inability to effectively separate device impedance from parasitic resistance in scribe lines.
Innovation Solution
Incorporating monitor structures with specific transistor configurations in scribe lines adjacent to dies, allowing for impedance measurements at different bias voltages to isolate device impedance from parasitic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional impedance measurement techniques are used without monitor structures in scribe lines, then the measurement process is simpler, but the measurement precision is poor due to inability to separate device impedance from parasitic resistance
Solution Approach 1:
The patent divides the impedance measurement into separate components by creating dedicated monitor structures in scribe lines. These monitor structures are segmented from the main die areas and are specifically designed to measure parasitic resistance, allowing the device impedance to be isolated and measured separately with high precision.
Solution Approach 2:
The monitor structures act as intermediary elements between the test equipment and the device under test. These intermediate structures with known geometries and configurations serve as mediators that enable the separation and measurement of parasitic resistance components, thereby improving the overall impedance measurement precision.
2Measurement precision
If monitor structures with multiple gate regions are added to scribe lines, then the ability to separate device impedance from parasitic resistance improves, but the manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by creating monitor structures with specific, controlled geometries in the scribe line areas. These local structures have defined gate regions, source/drain configurations, and dimensions that are optimized for measuring specific parasitic resistance components, while the rest of the wafer maintains its normal fabrication process.
Solution Approach 2:
The monitor structures are fabricated in advance during the wafer fabrication process, before the main device testing. This preliminary creation of dedicated measurement structures allows the parasitic resistance to be characterized and separated from device impedance early in the process, simplifying subsequent measurements.
Data Source
AI summary
In a described example, a semiconductor wafer can include a first monitor structure in a scribe line adjacent to a die, the first monitor structure including a first source region, a first drain region, and a first gate region. The first gate region can include a first elongated finger extending longitudinally between the first source region and the first drain region, as viewed from a top plan view. The semiconductor wafer can include a second monitor structure in the scribe line, the second monitor structure including one or more second source regions, one or more second drain regions, and a plurality of second gate regions. The second gate regions can include a second elongated finger extending longitudinally over a respective region of the die between the one or more second source regions and the one or more second drain regions, as viewed from the top plan view.