Monitoring Processor Anomaly Detection for Multi-Core Latency
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Solution Overview
Problem
In critical systems like aircraft and safety-related applications, multi-core processors face challenges in maintaining short and consistent latency for data access, ensuring failure safety, and detecting anomalies to prevent unpredictable behavior due to competing applications.
Innovation Solution
A processor system with an application processor and a monitoring processor, where the monitoring processor uses a look-up table to compare the progression of hardware performance events with target profiles, enabling continuous monitoring and countermeasures to ensure safe operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple applications are executed on multi-core processors, then processing power and productivity are improved, but latency periods for data access increase and become unpredictable
Solution Approach 1:
The system performs preliminary actions by establishing expected performance profiles before anomalies occur. The monitoring processor records and stores performance event progressions during normal operation, creating baseline profiles that define acceptable latency ranges. When actual performance deviates from these pre-established profiles, anomalies are detected and countermeasures can be taken promptly.
Solution Approach 2:
The system implements continuous feedback by monitoring actual performance event progressions against expected profiles in real-time. The monitoring processor compares recorded performance data with stored baseline profiles and provides feedback signals when deviations exceed thresholds, enabling dynamic response to latency issues while multiple applications run concurrently.
2Reliability
If safety-related applications are monitored continuously, then reliability and safety integrity are improved, but device complexity increases
Solution Approach 1:
The monitoring processor serves multiple functions within a single component: it records performance events, stores baseline profiles, compares actual performance against expectations, detects anomalies, and triggers countermeasures. This multi-functional design achieves comprehensive safety monitoring without proportionally increasing system complexity.
Solution Approach 2:
The system performs self-monitoring by having the monitoring processor automatically compare performance events against expected profiles and detect its own anomalies. The monitoring function is integrated into the processor system itself rather than requiring external monitoring equipment, reducing overall system complexity while maintaining safety integrity.
3Difficulty of detecting and measuring
If performance counters and monitoring logic are added to processors, then anomaly detection capability is improved, but manufacturing complexity increases
Solution Approach 1:
The system merges the monitoring and performance counting functions directly into the processor architecture itself. The monitoring processor is integrated with the application processor cores, sharing hardware resources and execution pathways. This consolidation enables advanced anomaly detection while avoiding the complexity of separate external monitoring systems.
Data Source
AI summary
A processor system includes an application processor, which has a processor core and hardware performance counters, and a monitoring processor, which is coupled to the application processor by a data transmission interface. The monitoring processor has a look-up table, in which target performance profiles of the progression over time of performance events of the hardware performance counters are stored for an application which is to be executed on the application processor and monitored. The monitoring processor has an evaluating logic which is linked to the look-up table and is configured to record the progression over time of performance events of the hardware performance counters during the execution of the application to be monitored on the application processor and to compare the progression with the target performance profiles stored in the look-up table.