3D Memory Structure With Monocrystalline Channels and Shorter Interconnects
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Solution Overview
Problem
Current 3D integrated circuit technologies face challenges with wire performance and power consumption due to the degradation of interconnects as transistors are scaled down, and existing 3D memory structures often use poly-silicon channels that suffer from higher cell-to-cell performance variations and lower drive than monocrystalline channels.
Innovation Solution
The development of multilayer semiconductor devices with self-aligned transistors formed using a single lithography step, featuring monocrystalline channels and hybrid bonding techniques such as oxide-to-oxide and metal-to-metal bonding, to construct 3D memory structures that reduce construction costs and improve device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are scaled down to improve transistor performance and density, then transistor density improves, but wire performance degrades and power consumption increases
Solution Approach 1:
The patent transitions from 2D planar transistor arrangements to 3D vertically-stacked transistor structures. Multiple transistor layers are stacked vertically with interconnect layers positioned between them, enabling higher transistor density without proportionally increasing wire lengths. This dimensional change allows transistors to be placed closer in the vertical dimension while maintaining reasonable horizontal wire lengths, thus improving density without the same degree of power consumption increase that would occur with continued 2D scaling.
2Ease of manufacture
If poly-silicon is used for memory cell channels to simplify manufacturing, then manufacturing complexity is reduced, but cell-to-cell performance variation increases and drive current decreases
Solution Approach 1:
The patent changes the material parameter of the channel from poly-silicon to monocrystalline silicon. This parameter change improves carrier mobility and reduces performance variation between cells, as monocrystalline silicon has more uniform electrical properties. The manufacturing process is adjusted accordingly to grow monocrystalline silicon channels, potentially using techniques like selective epitaxial growth, which maintains manufacturing feasibility while achieving superior device performance and uniformity.
3Manufacturing precision
If multiple lithography steps are used to form self-aligned transistors across multiple layers, then transistor alignment precision improves, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the formation of self-aligned transistor structures across multiple layers into a single lithography step. By designing the lithography pattern to simultaneously define transistor regions in multiple stacked layers, the process eliminates the need for separate lithography steps for each layer. This merging approach maintains precise alignment through self-alignment mechanisms while significantly reducing fabrication process complexity and cost.
Solution Approach 2:
The lithography step is designed to perform multiple functions simultaneously: defining transistor regions in the first layer, defining transistor regions in the second layer, and establishing self-alignment relationships between layers. This multi-functional lithography approach reduces the total number of lithography steps required while maintaining the precision benefits of self-alignment.
Data Source
AI summary
A method to process a 3D device, the method including: providing a first substrate including a first level including a first single crystal silicon layer and a plurality of first transistors; providing a second substrate including a second level including a second single crystal silicon layer; performing an epitaxial growth of a SiGe layer on top of the second single crystal silicon layer; performing an epitaxial growth of a third single crystal silicon layer on top of the SiGe layer; forming a plurality of third transistors including the third single crystal silicon layer; forming a plurality of metal layers interconnecting the plurality of third transistors; and then performing a hybrid bonding of the second level onto the first level.