Monocrystalline 3D DFM Pillar Memory Without DRAM Capacitors
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Solution Overview
Problem
Current 1T1C DRAM devices face challenges with increased leakage currents, power consumption, and decreased retention times, making it difficult to manufacture small-node capacitors, while capacitor-free DRAM devices require improvements in integration and operation.
Innovation Solution
A capacitor-free monocrystalline dynamic random-access memory device is developed, featuring a monolithic vertical pillar made of monocrystalline material surrounded by an insulating layer, with gate contacts configured to address and program the pillar, reducing defects and leakage currents, and increasing charge retention times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If 1T1C DRAM devices use small-node capacitors to retain charge, then charge retention is improved, but manufacturing difficulty increases due to increased current leakage and decreased retention times
Solution Approach 1:
The patent removes the capacitor component entirely from the memory cell structure, replacing the traditional 1T1C architecture with a capacitor-free design. This extraction of the problematic capacitor element eliminates the manufacturing difficulties associated with small-node capacitors while maintaining charge retention functionality through an alternative mechanism involving a single transistor with modified structure and operation
Solution Approach 2:
The patent changes the operational parameters and structure of the single transistor, transitioning from conventional transistor operation to a mode that enables charge retention without a capacitor. This involves modifying the transistor structure (e.g., using surrounding gate structures) and changing how the transistor stores and retains charge, thereby achieving capacitor-free charge retention
2Quantity of substance
If 1T1C DRAM devices use small-node capacitors, then charge storage is improved, but leakage current increases
Solution Approach 1:
By removing the capacitor from the memory cell, the patent eliminates the source of leakage current associated with capacitor structures. The charge storage function is transferred to the transistor itself, which has different leakage characteristics and can be engineered to have lower leakage through the surrounding gate structure
Solution Approach 2:
The patent copies the charge storage function from the capacitor to the transistor structure. Instead of using a separate capacitor component, the transistor is designed to perform both switching and charge storage functions, effectively copying the storage capability to a different component that has lower leakage
3Duration of action of stationary object
If 1T1C DRAM devices use small-node capacitors, then charge retention is improved, but power consumption increases
Solution Approach 1:
Removing the capacitor eliminates the energy losses associated with capacitor charging and discharging cycles. The capacitor-free design reduces the energy required for write operations since there is no capacitor to charge, and reduces refresh power consumption by using the transistor's inherent charge retention capability
Solution Approach 2:
The transistor structure is designed to self-retain charge without requiring external capacitor support. The surrounding gate structure creates an electric field that confines carriers within the channel, enabling the transistor to service its own charge retention needs without additional components
4Ease of manufacture
If capacitor-free DRAM devices are implemented, then manufacturing integration is simplified, but operational performance needs improvement
Solution Approach 1:
The patent merges the functions of the transistor and capacitor into a single transistor structure. The surrounding gate transistor is designed to perform both the switching function and the charge storage function that were previously separated between transistor and capacitor components, simplifying manufacturing while maintaining operational performance
Solution Approach 2:
The patent employs composite material structures in the transistor, such as combining different semiconductor materials or using heterostructure designs in the surrounding gate. This allows the single transistor to achieve the complex functionality of charge storage and switching that previously required separate capacitor and transistor components
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution decreases defects, leakage current, and power consumption, while increasing charge retention times and reducing refresh rates, enabling more efficient manufacturing and operation of 3D memory devices.
Implementation Method 1
the pillar can be configured to store an electrical charge
Data Source
AI summary
A three-dimensional (3D) memory device includes a memory cell, a top contact coupled to the memory cell, and a bottom contact coupled to the memory cell. The memory cell can include a pillar, an insulating layer surrounding the pillar, a first gate contact surrounding a first portion of the insulating layer, and a second gate contact surrounding a second portion of the insulating layer. The pillar can be configured to store an electrical charge. The pillar can be a monocrystalline material. The 3D memory device can utilize dynamic flash memory (DFM), decrease defects, increase manufacturing efficiency, decrease leakage current, decrease junction current, decrease power consumption, increase storage density, increase charge retention times, and decrease refresh rates.