Monocrystalline Layer Stack for Stable 3D GAA Transistor Etching
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Solution Overview
Problem
The mechanical stability of multilayer stacks in GAA transistor technology is limited by compressive stress in SiGe layers, leading to dislocation emission and reduced memory capacity or current density in 3D microelectronic devices, due to the high Ge concentration required for etch selectivity.
Innovation Solution
A stack comprising unintentionally doped silicon, SiGe, and P-doped silicon or SiGe layers, where the P-doped layers replace those with high Ge concentration, enhancing etch selectivity and allowing greater thickness without dislocation generation, thereby improving memory density and active layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high Ge concentration SiGe layers are used to ensure sufficient etch selectivity, then etch selectivity is improved, but mechanical stability deteriorates due to increased compressive stress and dislocation emission
Solution Approach 1:
The patent changes the doping parameter of silicon layers from unintentionally doped to P-doped, which fundamentally alters the etch selectivity mechanism. P-doped silicon layers provide sufficient etch selectivity against SiGe layers without requiring high Ge concentration, thereby maintaining mechanical stability while achieving the desired etching performance
Solution Approach 2:
The patent creates a composite multilayer stack structure alternating between P-doped silicon layers and SiGe layers. This composite structure leverages the complementary properties of doped silicon (high etch selectivity, mechanical stability) and SiGe (semiconductor functionality) to resolve the contradiction between etch selectivity and mechanical stability
2Quantity of substance
If the total thickness of the stack is increased to achieve higher memory density or current density, then memory capacity or current density is improved, but mechanical stability deteriorates due to exceeding critical thickness and generating dislocations
Solution Approach 1:
By changing the doping parameter of silicon layers to P-doped, the patent enables increased total stack thickness without dislocation generation. The P-doping provides mechanical reinforcement and stress management, allowing the stack to exceed previous thickness limits while maintaining integrity and achieving higher memory density
3Quantity of substance
If the number of alternating layers is increased to improve memory density, then memory capacity is improved, but mechanical stability deteriorates due to accumulated compressive stress
Solution Approach 1:
The patent constructs a composite multilayer stack with alternating P-doped silicon and SiGe layers. The P-doped silicon layers act as mechanical reinforcement layers that counterbalance the compressive stress in SiGe layers, enabling a higher number of alternating layers to be stacked while maintaining overall mechanical stability and achieving improved memory density
Data Source
AI summary
Stack of layers of monocrystalline materials suitable for producing microelectronic devices with 3D architecture comprising transistors, including several first layers of monocrystalline material, several second layers of monocrystalline material different from that of the first layers, and at least one third layer of monocrystalline material different from those of the first and second layers, wherein: a first of the monocrystalline materials of the first, second and third layers corresponds to intrinsic silicon; a second of the monocrystalline materials of the first, second and third layers corresponds to intrinsic SiGe; a third of the monocrystalline materials of the first, second and third layers corresponds to p-doped silicon or p-doped SiGe.