Monolayer Thin Film Capacitor Via-Connected Electrodes
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Solution Overview
Problem
Conventional multilayer ceramic capacitors face limitations in miniaturization and high capacity due to bulk manufacturing processes, and there is a need for a method to significantly reduce the height and occupancy area of monolayer thin film capacitors while simplifying their manufacturing process.
Innovation Solution
A monolayer thin film capacitor design featuring a bottom electrode, a dielectric layer, a top electrode, a first via penetrating through the dielectric layer, a second via with a greater width or diameter, and a connection electrode on the inner sides of both vias, which are electrically connected to the bottom electrode and insulated from the top electrode, along with a manufacturing method that includes forming these components using metal layers and etching processes to reduce the overall thickness and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional multilayer ceramic capacitor is manufactured by stacking dozens or hundreds of ceramic sheets, then high capacity can be achieved, but the height and occupancy area cannot be significantly reduced
Solution Approach 1:
The patent transitions from a three-dimensional stacked structure (multiple ceramic sheets) to a two-dimensional planar structure (single layer with patterned electrodes). This dimensional change allows the capacitor to achieve high capacity through increased planar area utilization rather than vertical stacking, thereby significantly reducing height while maintaining or improving capacity.
Solution Approach 2:
The patent divides the capacitor into distinct functional layers (dielectric layer, first electrode layer, second electrode layer) with patterned electrode arrangements. This segmentation allows for optimized area utilization and capacity distribution within a single layer, eliminating the need for multiple stacked layers while achieving high capacity.
2Ease of manufacture
If a conventional multilayer ceramic capacitor is manufactured by stacking ceramic sheets with electrode paste, then electrodes can be formed on both ends, but the manufacturing process complexity increases
Solution Approach 1:
The patent combines multiple manufacturing steps into a simplified process. Instead of stacking multiple ceramic sheets and forming electrodes on each, the invention forms all electrodes within a single dielectric layer using a unified electrode pattern design, thereby reducing manufacturing process complexity.
Solution Approach 2:
The patent extracts and eliminates unnecessary components from the conventional structure. By removing the need for multiple ceramic sheets and intermediate electrode layers, the invention simplifies the manufacturing process while maintaining electrode functionality through a streamlined single-layer architecture.
3Area of stationary object
If a board embedded-type capacitor is designed to reduce occupancy area and height, then miniaturization is achieved, but the manufacturing process becomes more complex
Solution Approach 1:
The patent employs a planar two-dimensional electrode arrangement within a single layer, maximizing area utilization efficiency. This dimensional approach enables significant occupancy area reduction for board embedding applications while keeping the manufacturing process simple through unified layer formation.
Solution Approach 2:
The patent creates a universal capacitor structure that simultaneously achieves miniaturization, high capacity, and simplified manufacturing. The single-layer patterned electrode design serves multiple functions: reducing occupancy area, minimizing height, and simplifying the manufacturing process, making it universally applicable for embedded applications.
Data Source
AI summary
A monolayer thin film capacitor includes: a bottom electrode; a top electrode; a dielectric layer disposed between the bottom electrode and the top electrode; a first via formed in the dielectric layer so as to penetrate through the dielectric layer; a second via formed in the top electrode so as to penetrate through the top electrode and having a greater width or a greater diameter than that of the first via; and a connection electrode disposed on inner sides of the first and second vias, electrically connected to the bottom electrode, and electrically insulated from the top electrode.