Self-Limiting Monolayer Doping for III-V Semiconductor Junctions
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Solution Overview
Problem
Existing techniques for doping III-V compound semiconductors, such as ion implantation, face challenges in controlling post-growth dopant profiles and inducing crystal damage, which affects the performance of nanoscale devices like InAs nanowire transistors.
Innovation Solution
The use of self-limiting monolayer and gas-phase doping techniques to introduce dopants onto the surface of III-V semiconductor substrates, allowing for precise control of dopant distribution and avoiding lattice damage, enabling the formation of ultrashallow junctions and p-n junctions in devices like diodes and transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional ion implantation is used for doping III-V compound semiconductors, then dopant introduction is achieved, but crystal damage is induced and stoichiometry is altered
Solution Approach 1:
The patent replaces the mechanical ion implantation process with a chemical surface-mediated diffusion process. Dopants are first deposited as a monolayer on the semiconductor surface, then introduced into the crystal lattice through thermal diffusion at relatively low temperatures (400-600°C), avoiding the high-energy mechanical impact that causes crystal damage while maintaining effective dopant incorporation
Solution Approach 2:
The patent introduces a surface monolayer as an intermediary between the dopant source and the crystal lattice. This surface-mediated approach allows dopants to be gradually incorporated into the crystal structure through diffusion, rather than direct high-energy implantation, thereby preserving crystal integrity while achieving desired doping profiles
2Quantity of substance
If ion implantation is used to dope nanoscale III-V devices, then doping is achieved, but severe crystal damage occurs resulting in In atom clustering
Solution Approach 1:
The patent fundamentally changes the process parameters from high-energy ion implantation to low-energy surface deposition followed by low-temperature thermal diffusion (400-600°C). This parameter change prevents the severe crystal damage and In atom clustering that occur with conventional ion implantation, maintaining nanoscale structural integrity while achieving effective doping
Solution Approach 2:
The patent replaces the mechanical ion implantation process with a chemical surface-mediated diffusion process, eliminating the high-energy impact that causes In atom clustering and crystal structure degradation in nanoscale devices
3Ease of manufacture
If post-growth patterned doping is desired for device fabrication, then device integration is improved, but conventional ion-implantation techniques are not compatible with nanoscale III-V semiconductors
Solution Approach 1:
The patent segments the doping process into distinct stages: (1) selective surface preparation and monolayer deposition on patterned regions, (2) thermal diffusion to introduce dopants, and (3) selective removal of unreacted dopant. This segmentation enables precise spatial control for patterned doping while using gentle processes compatible with nanoscale III-V structures
Solution Approach 2:
The patent uses surface monolayers as intermediaries that enable selective, patterned doping through chemical processes rather than high-energy ion implantation, making the process compatible with nanoscale III-V semiconductor fabrication
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These methods allow for high areal dose and uniformity of dopants, forming abrupt and electrically active junctions, improving device performance by reducing junction leakage and enhancing dopant activation, as demonstrated in InAs-based devices.
Implementation Method 1
a thermal annealing process is performed to drive the sulfur into the substrate to a desired junction depth
Implementation Method 2
performing Zn gas-phase doping through surface diffusion
Data Source
AI summary
Compound semiconductor devices and methods of doping compound semiconductors are provided. Embodiments of the invention provide post-deposition (or post-growth) doping of compound semiconductors, enabling nanoscale compound semiconductor devices including diodes and transistors. In one method, a self-limiting monolayer technique with an annealing step is used to form shallow junctions. By forming a sulfur monolayer on a surface of an InAs substrate and performing a thermal annealing to drive the sulfur into the InAs substrate, n-type doping for InAs-based devices can be achieved. The monolayer can be formed by surface chemistry reactions or a gas phase deposition of the dopant. In another method, a gas-phase technique with surface diffusion is used to form doped regions. By performing gas-phase surface diffusion of Zn into InAs, p-type doping for InAs-based devices can be achieved. Both bulk and nanowire devices using compound semiconductors can be fabricated using these surface and gas-phase doping processes.