Monolayer Doping for Self-Aligned Transistor Source/Drain Regions
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Solution Overview
Problem
Current methods for forming transistors and memory cells often result in defects and crystal lattice damage due to ion implantation, and struggle with accurate vertical self-alignment of source/drain regions, leading to issues like gate-induced drain leakage.
Innovation Solution
The method involves forming a gate construction with a conductive gate material and a gate insulator, followed by monolayer doping of opposing sidewall surfaces, where dopants are diffused into the semiconductor material to create vertically-self-aligned source/drain regions without ion implantation, using a process that includes chemical etching and rapid thermal annealing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion implantation is used to form source/drain regions, then doping can be achieved, but defects and crystal lattice damage occur
Solution Approach 1:
The patent replaces the mechanical ion implantation process with a chemical diffusion process. Dopant atoms are introduced through chemical vapor deposition or molecular beam epitaxy, allowing dopants to diffuse into the semiconductor lattice through thermal energy rather than mechanical impact, thereby avoiding crystal lattice damage while achieving precise doping profiles
Solution Approach 2:
The patent changes the physical state and introduction method of dopant atoms from high-energy ionized state to low-energy atomic state. By controlling temperature, pressure, and gas flow parameters during chemical deposition, the dopants are introduced in a controlled manner that prevents lattice damage while maintaining doping precision
2Productivity
If conventional doping methods are used, then source/drain regions can be formed, but vertical self-alignment is inaccurate leading to gate-induced drain leakage
Solution Approach 1:
The patent performs preliminary formation of the gate structure with precisely defined sidewalls before introducing dopants. The gate sidewalls serve as pre-established alignment references that guide the subsequent dopant diffusion process, ensuring accurate vertical self-alignment of source/drain regions relative to the gate without requiring additional alignment steps
Solution Approach 2:
The gate structure itself serves as the alignment reference for dopant placement. The dopant diffusion is confined by the gate sidewalls, which automatically define the lateral boundaries of source/drain regions. This self-aligning mechanism eliminates the need for separate alignment procedures and prevents gate-induced drain leakage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces defects and crystal lattice damage, achieves accurate vertical self-alignment of source/drain regions, and minimizes gate-induced drain leakage, resulting in more uniform doping and improved transistor performance.
Implementation Method 1
dopants are diffused into the semiconductor material to create vertically-self-aligned source/drain regions
Implementation Method 2
using a process that includes chemical etching and rapid thermal annealing
Data Source
AI summary
An embodiment of the invention comprises a method of forming a transistor comprising forming a gate construction having an elevationally-outermost surface of conductive gate material that is lower than an elevationally-outer surface of semiconductor material that is aside and above both sides of the gate construction. Tops of the semiconductor material and the conductive gate material are covered with masking material, two pairs of two opposing sidewall surfaces of the semiconductor material are laterally exposed above both of the sides of the gate construction. After the covering, the semiconductor material that is above both of the sides of the gate construction is subjected to monolayer doping through each of the laterally-exposed two opposing sidewall surfaces of each of the two pairs and forming there-from doped source/drain regions above both of the sides of the gate construction.