Monolithic 3D Integrated Circuit With Buried Vias for Dense Stacking
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Solution Overview
Problem
Current miniaturization techniques for integrated circuits (ICs) are reaching their limits in two-dimensional space, necessitating a move to three-dimensional integration to achieve higher device packing density, lower interconnect delay, and lower costs.
Innovation Solution
The development of monolithic three-dimensional integrated circuits (3DICs) that vertically stack electronic components and connections within multiple tiers on a single die using buried vias (BVs), eliminating the need for precise alignment and through silicon vias (TSVs, which are larger and less efficient.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional integrated circuits are used to achieve higher device packing density, then integration density is improved, but manufacturing complexity increases due to alignment requirements
Solution Approach 1:
The patent introduces an intermediary alignment marker system that mediates between stacked dies. These markers are formed in the interconnect layers and serve as reference points for alignment, eliminating the need for complex direct alignment between dies. The markers act as a intermediate reference framework that simplifies the alignment process while enabling high-density 3D integration.
Solution Approach 2:
The alignment markers are formed in advance during the interconnect layer formation process, before the stacking operation. This preliminary action ensures that alignment references are already in place when dies are stacked, eliminating the need for complex real-time alignment procedures and reducing manufacturing complexity.
2Reliability
If through silicon vias (TSVs) are used for vertical interconnection, then electrical coupling is achieved, but die area is increased and manufacturing precision requirements are heightened
Solution Approach 1:
The patent extracts the alignment reference function from the TSV structure itself and separates it into distinct alignment markers formed in the interconnect layers. This allows TSVs to be smaller and more densely packed since they no longer need to incorporate alignment features, thereby reducing die area while maintaining reliable electrical coupling.
Solution Approach 2:
The patent applies different functions to different parts of the vertical interconnection structure: TSVs are optimized for electrical coupling with smaller diameters, while separate alignment markers provide the reference function. This local differentiation allows each component to be optimized for its specific function, reducing overall die area while maintaining coupling reliability.
3Manufacturing precision
If precise alignment methods are used for stacked dies, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent uses simple geometric patterns (such as rings or cross-hairs) as alignment markers that can be easily copied and reproduced across multiple dies. These markers are formed using standard photolithography processes, avoiding the need for expensive specialized alignment equipment or complex procedures, thereby reducing manufacturing cost while maintaining precision.
4Loss of time
If more metal layers are added for vertical stacking, then interconnect delay is reduced, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar interconnects to three-dimensional vertical interconnects by stacking dies with interconnect layers in between. This dimensional change allows signals to travel shorter vertical distances rather than long horizontal paths, reducing interconnect delay. The systematic formation of interconnect layers between stacked dies creates efficient vertical routing without excessive complexity.
Data Source
AI summary
A monolithic three dimensional integrated circuit is provided. The monolithic three dimensional integrated circuit includes a first cell layer having a first cell having a first active component of the monolithic three dimensional integrated circuit. A second layer having a second cell including a second active component. The second cell layer is formed vertically above the first cell layer. The first cell layer having the first active component and the second cell layer having the second active component are formed on a single die. The first cell has a smaller metal pitch than the second cell. A buried via electrically couples the first active component of the first cell of the first cell layer with the second active component of the second cell of the second cell layer.