Monolithic 3D IC CAD Placement via Layer Partitioning
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Solution Overview
Problem
Current CAD tools face challenges in optimizing the design of monolithic three-dimensional integrated circuits, as they are not adequately equipped to leverage the dense inter-layer connectivity and disparate characteristics of layers in monolithic 3D technology, which differs significantly from stacked-layer processes that rely on large Through-Silicon Vias.
Innovation Solution
The solution involves extending CAD tool functionality to perform partitioning and placement using 2D placers and routers, optimizing the placement of objects across multiple strata based on their characteristics, and leveraging the dense inter-layer connectivity to improve the physical proximity of objects in 3D space, rather than relying on TSVs, by partitioning logic and memory layers and using virtual decoder representations for efficient placement and routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional CAD tools are used for monolithic 3D IC design, then the design process can be completed, but the tools cannot adequately leverage dense inter-layer connectivity and disparate layer characteristics, resulting in suboptimal placement and routing
Solution Approach 1:
The design flow is segmented into distinct phases: partitioning logic and memory to different strata, placing logic on first strata, placing memory on second strata, and routing inter-strata connections. This segmentation allows each phase to be optimized independently for monolithic 3D characteristics.
Solution Approach 2:
The invention transitions from traditional 2D planar design to 3D stacked design by utilizing multiple strata (layers) vertically stacked. Logic and memory are placed on different strata, and inter-layer connections are established through vertical vias, leveraging the third dimension to improve connectivity and reduce wire length.
2Reliability
If Through-Silicon Vias (TSVs) are used for inter-layer connections, then layer connectivity can be achieved, but the connections become large and expensive, reducing scalability
Solution Approach 1:
The invention uses standard semiconductor fabrication processes to create inter-layer connections, effectively copying proven 2D IC connection methodologies to the 3D monolithic context. This avoids the need for novel, complex TSV structures while maintaining connectivity reliability.
Solution Approach 2:
The invention changes the connection parameters by using smaller, more scalable via structures instead of large TSVs. The via dimensions and fabrication parameters are optimized for monolithic 3D processes, enabling higher density and lower cost inter-layer connections.
3Ease of manufacture
If logic and memory are placed on the same layer, then routing is simpler, but inter-layer connectivity density and proximity are reduced
Solution Approach 1:
Logic and memory functions are segmented onto different strata, allowing each to be optimized for its specific requirements while enabling dense vertical interconnections between the strata through aligned via structures.
Solution Approach 2:
By separating logic and memory onto different vertical strata, the invention utilizes the third dimension to achieve both high inter-layer connectivity density and functional separation, overcoming the limitations of planar 2D placement.
Data Source
AI summary
A method of designing a 3D Integrated Circuit including: partitioning at least one design into at least a first and a second level, where the first level includes logic and the second level includes memory; then performing a first placement of the second level using a placer executed by a computer, the placer is a part of a Computer Aided Design tool, where the 3D Integrated Circuit includes a plurality of connections between the first level and the second level; and performing a second placement of the first level based on the first placement, where memory includes a first memory array, the logic includes a first logic circuit configured so as to write data to first memory array. Performing the first placement includes placing the first memory array, and where performing the second placement includes placing the first logic circuit based on the first placement of the first memory array.