Monolithic 3D Integrated Circuits with Vertical Memory Components
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Solution Overview
Problem
Conventional two-dimensional integrated circuits face challenges in miniaturization and power consumption due to complex routing requirements and long access lines in memory banks, leading to increased resistive-capacitive delay and metal routing congestion.
Innovation Solution
The implementation of monolithic three-dimensional integrated circuits with vertical memory components and tight-pitched monolithic intertier vias reduces inter-block wire lengths, eliminating the need for long horizontal crossbars and repeaters, thereby decreasing RC delay and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional two-dimensional integrated circuit designs are used with increased number of memory bit cells, then memory capacity increases, but access line length increases leading to increased RC delay
Solution Approach 1:
The patent transitions from two-dimensional to three-dimensional integrated circuit architecture, stacking memory bit cells vertically across multiple tiers. This dimensional change allows memory capacity to increase while keeping access line lengths short, as all bit cells within a bank are accessible through vertical vias rather than long horizontal routing lines.
2Quantity of substance
If more memory bit cells are assembled into memory banks, then memory capacity increases, but routing complexity and metal route congestion increase
Solution Approach 1:
By stacking memory tiers vertically and using through-silicon vias for interconnections, the patent eliminates the need for complex planar routing networks. The vertical architecture provides direct access to all bit cells in a bank through the column selection lines, dramatically simplifying the routing topology while supporting high memory capacity.
Solution Approach 2:
The memory array is segmented into multiple banks, with each bank containing bit cells from different tiers. This segmentation allows independent access to each bank through dedicated row and column selection lines, reducing routing complexity by localizing the interconnection requirements for each bank.
3Quantity of substance
If longer access lines are used to reach more memory bit cells, then memory capacity increases, but resistive-capacitive delay increases
Solution Approach 1:
The three-dimensional architecture with vertical stacking and via-based interconnections eliminates long horizontal access lines. All bit cells within a memory bank are accessed through short vertical column selection lines and row selection lines, minimizing RC delay regardless of the number of bit cells in the bank.
4Adaptability or versatility
If crossbars are used for inter-block communication in 2D designs, then connectivity is improved, but significant routing resources are consumed
Solution Approach 1:
The patent replaces planar crossbar architectures with a three-dimensional memory structure where inter-block communication is achieved through vertical stacking and selective tier access. This eliminates the need for large crossbars while maintaining full connectivity between memory blocks through the vertical interconnect structure.
Data Source
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AI summary
Monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) with vertical memory components (64) are disclosed. A 3D memory crossbar (66) architecture with tight-pitched vertical monolithic intertier vias (MIVs) (68) for inter-block routing and multiplexers (70) at each tier (62) for block access is used to shorten overall conductor length and reduce resistive-capacitive (RC) delay. Elimination of such long crossbars reduces the RC delay of the crossbar and generally improves performance and speed. Further, elimination of the long horizontal crossbars makes conductor routing easier. The MIVs, with their small run-length, can work without the need for repeaters (unlike the long crossbars), and control logic may be used to configure the memory banks based on use.