Monolithic 3D IC Layout Using Dense Inter-Layer Connectivity
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Solution Overview
Problem
Existing CAD tools struggle to optimize the placement and routing of transistors and wires in monolithic 3D integrated circuits, as they are designed for stacked-layer processes with large Through-Silicon Vias (TSVs), failing to leverage the dense inter-layer connectivity and disparate characteristics of monolithic 3D technology.
Innovation Solution
The method involves using 2D placers and routers within CAD tools to optimize the placement and routing of transistors and wires across multiple strata in monolithic 3D integrated circuits, considering the dense inter-layer connectivity and potential differences in characteristics between layers, and incorporating partitioning and placement strategies to balance areas and improve physical proximity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If existing CAD tools are used for monolithic 3D IC design, then the design process can be automated, but the tools fail to optimize placement and routing due to being designed for stacked-layer processes with large TSVs
Solution Approach 1:
The patent modifies the design parameters and constraints in the CAD tool to account for monolithic 3D IC characteristics, including dense inter-layer connectivity and disparate layer characteristics, rather than using parameters optimized for TSV-based stacked layers
Solution Approach 2:
The patent applies different placement and routing strategies to different strata based on their specific characteristics, allowing each layer to be optimized according to its local requirements rather than applying a uniform approach across all layers
2Productivity
If dense inter-layer connectivity is leveraged in monolithic 3D ICs, then design efficiency is improved, but existing CAD tools cannot properly utilize this connectivity due to being designed for large TSVs
Solution Approach 1:
The patent extends the traditional 2D placement and routing approach to three dimensions by incorporating vertical connectivity between strata, allowing design tools to exploit the additional dimensional space provided by dense inter-layer connections in monolithic 3D ICs
3Length of stationary object
If partitioning and placement strategies are used to balance areas across strata, then physical proximity is improved, but the complexity of the placement process increases
Solution Approach 1:
The patent divides the monolithic 3D IC design into separate strata that can be independently partitioned and placed, then integrated through defined interfaces, managing complexity by breaking down the overall placement problem into smaller, more manageable segments
Data Source
AI summary
Methods of designing a 3D Integrated Circuit including: partitioning at least one design into at least two levels, a first level and a second level, where the first level includes first transistors, where the second level includes second transistors is on top of the first level; providing placement data of the second level; performing a placement of the first level using a placer program executed by a computer, where the placement of the first level is based on the placement data, where the placer is part of a Computer Aided Design (CAD) tool, and where the first level includes first routing layers; performing a routing of the first level using a router {part of the CAD tool or another CAD tool) executed by a computer, where at least one metal routing layer is disposed in-between the first transistors and the second transistors, and the second level includes repeating structures.