Monolithic 3D IC Tiers for Space-Efficient System-on-Chip Integration
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Solution Overview
Problem
Current system-on-chip (SOC) solutions face challenges in miniaturization due to the difficulty in integrating disparate components with different physical requirements, such as analog and digital components, within a single integrated circuit, leading to space inefficiencies and the need for external wiring in die stacking arrangements.
Innovation Solution
The implementation of monolithic three-dimensional (3D) integrated circuit (IC) technology, which allows for customization of layers and short interconnections between tiers using monolithic intertier vias (MIV), enabling a complete SOC within a single IC by distributing various functional elements like computation, digital processing, and RF signal processing across multiple tiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If die stacking arrangements are used to integrate analog and digital components, then functional integration is improved, but space efficiency deteriorates due to external wiring requirements and ziggurat shape
Solution Approach 1:
The patent merges analog and digital components into a single monolithic 3D IC structure, eliminating the need for separate dies and external wiring. All functional elements are integrated within one chip, achieving both high functional integration and space efficiency by removing the ziggurat shape problem.
Solution Approach 2:
The patent transitions from 2D planar integration to 3D vertical integration, stacking functional layers in the third dimension. This allows multiple functional elements to be integrated within a small footprint area, dramatically improving space efficiency while maintaining high functional integration.
2Adaptability or versatility
If external wiring is used to couple analog and digital chips, then component integration is improved, but area consumption increases due to conductor space
Solution Approach 1:
The patent combines interconnection structures directly within the monolithic 3D IC, eliminating external wiring. Conductors are formed as integrated vias and interconnect layers within the chip structure, removing the need for separate external conductor space.
Solution Approach 2:
The patent introduces monolithic intertier vias (MIV) as intermediary connection structures between stacked functional layers. These MIVs provide direct vertical interconnections within the chip, replacing external wiring and reducing area consumption.
3Productivity
If miniaturization is pursued to fit more functions in limited space, then functional density is improved, but integration of disparate components with different physical requirements becomes more difficult
Solution Approach 1:
The patent segments the integrated circuit into multiple functional layers stacked in the vertical dimension. Each layer can be independently designed and optimized for specific functions (analog, digital, RF, etc.), allowing disparate components with different physical requirements to coexist in the same chip without interfering with each other.
Solution Approach 2:
The patent applies local quality by allowing different regions and layers of the 3D IC to have different properties optimized for their specific functions. For example, RF layers can be designed with specific material compositions and geometries for radio frequency operation, while digital layers use standard CMOS processes, enabling high functional density while meeting diverse component requirements.
Data Source
AI summary
Embodiments disclosed in the detailed description include a complete system-on-chip (SOC) solution using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) integration technology. The present disclosure includes example of the ability to customize layers within a monolithic 3DIC and the accompanying short interconnections possible between tiers through monolithic intertier vias (MIV) to create a system on a chip. In particular, different tiers of the 3DIC are constructed to support different functionality and comply with differing design criteria. Thus, the 3DIC can have an analog layer, layers with higher voltage threshold, layers with lower leakage current, layers of different material to implement components that need different base materials and the like. Unlike the stacked dies, the upper layers may be the same size as the lower layers because no external wiring connections are required.