Monolithic 3D Image Sensor Stacking for Alignment and Parallel Readout
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current image sensors face challenges in achieving high efficiency due to the large area consumed by sensing circuits, which limits photodetector exposure and results in inefficient image capture, particularly with pixel sizes reaching the 1 μm range where alignment issues for through-silicon via technology become difficult, and CCD technology is hindered by sequential shifting of image information, leading to slow speed and low cell density.
Innovation Solution
The implementation of monolithic 3D integration using layer transfer technology to stack photodetectors and readout circuits, allowing for parallel data collection and reducing thermal budget constraints, and the use of two image sensor arrays with distinct distances and a beam-splitter or fast motor actuation to enhance image capture capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If through-silicon via technology is used to stack photodetectors and readout circuits, then integration density is improved, but alignment precision deteriorates at 1 μm pixel size range
Solution Approach 1:
The patent introduces an intermediary alignment layer with alignment marks between the photodetector array and readout circuit layer. This intermediary structure provides reference points for precise alignment during the stacking process, enabling accurate registration even at 1 μm pixel size where direct alignment would be difficult.
Solution Approach 2:
The patent performs preliminary alignment mark formation and positioning before the actual stacking operation. By pre-establishing alignment references on both layers to be stacked, the system enables high-precision alignment during bonding without requiring complex real-time adjustment mechanisms.
2Device complexity
If sensing circuits are integrated on the same chip as photodetectors, then device complexity is reduced, but photodetector exposure area decreases leading to lower image capture efficiency
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking, placing photodetectors and readout circuits on separate layers vertically. This dimensional change allows photodetectors to occupy the full chip surface area for maximum light exposure while readout circuits are positioned underneath, eliminating the area trade-off present in same-chip planar integration.
Solution Approach 2:
The patent segments the image sensor into functionally separate layers: a photodetector array layer for light detection and a readout circuit layer for signal processing. This segmentation allows each layer to be optimized independently for its specific function while maintaining high integration through vertical stacking.
3Measurement precision
If CCD technology is used for image sensing, then measurement precision is improved, but processing speed deteriorates due to sequential shifting
Solution Approach 1:
The patent uses three-dimensional stacking to place readout circuits directly beneath each photodetector element, enabling parallel readout of multiple pixels simultaneously. This vertical integration architecture eliminates the sequential charge shifting required by traditional CCDs, allowing all pixels to be read out in parallel while maintaining high measurement precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more efficient image capture by reducing the area required for sensing circuits, improving pixel size alignment, and allowing for parallel data processing, thereby enhancing image sensor performance and dynamic range without the limitations of sequential shifting.
Implementation Method 1
the oxide on the first level is bonded to the oxide on the second level
Data Source
AI summary
An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlaying oxide on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of semiconductor devices; a third level overlaying the second level, where the third level includes a plurality of image sensors, where the second level is bonded to the first level, where the bonded includes an oxide to oxide bond; and an isolation layer disposed between the second mono-crystal layer and the third level.