Monolithic 3D Integrated Circuit Memory Logic Integration
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Solution Overview
Problem
Monolithic integrated circuits face challenges in scaling due to limitations in planar dimensions, leading to inefficiencies in transistor density and bandwidth, particularly when integrating memory devices with logic devices using traditional methods like through silicon vias or wire bonding, which result in limited speed and increased package height.
Innovation Solution
A monolithic three-dimensional integrated circuit structure is developed, where a memory device layer is directly attached to an active circuitry layer using interconnects, eliminating the need for speed-limiting through silicon vias and achieving high bandwidth with a single die solution and thin package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through silicon vias are used to integrate memory die with logic die, then connection between memory and logic is achieved, but bandwidth is limited and package height increases
Solution Approach 1:
The patent transitions from planar integration to three-dimensional monolithic integration, stacking memory and logic circuits vertically on the same substrate. This dimensional change enables direct interconnection through multiple interconnect layers without requiring through-silicon vias, achieving higher bandwidth while maintaining compact package height through vertical stacking rather than lateral expansion
2Quantity of substance
If traditional planar scaling is continued, then device density increases, but manufacturing becomes impractical due to economic and physical limitations
Solution Approach 1:
The patent employs three-dimensional monolithic integration to achieve higher transistor density by stacking multiple circuit layers vertically on the same substrate. This approach avoids the manufacturing impracticalities of continued planar scaling by utilizing the third dimension, maintaining standard planar fabrication processes while achieving superior density through vertical stacking of active circuits and memory structures
3Adaptability or versatility
If memory die is integrated with logic die using conventional methods, then functional integration is achieved, but package height increases to at least two die
Solution Approach 1:
The patent merges memory circuits and logic circuits into a single monolithic three-dimensional integrated circuit on one substrate. By integrating both functional blocks vertically within the same die using shared interconnect layers and common substrate infrastructure, the design achieves full functional integration while reducing package height to a single die, eliminating the need for separate memory and logic packages
Solution Approach 2:
The patent utilizes vertical stacking in the third dimension to accommodate both memory and logic circuits on a single substrate. This dimensional approach allows multiple functional layers to be stacked vertically with interconnect layers providing electrical connections between levels, achieving complete functional integration within a single-die footprint and minimizing package height
Data Source
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AI summary
A method including forming a first substrate including an integrated circuit device layer disposed between a plurality of first interconnects and a plurality of second interconnects; coupling a second substrate including a memory device layer to the first substrate so that the memory device layer is juxtaposed to one of the plurality of first interconnects and the plurality of second interconnects; and removing a portion of the first substrate. An apparatus including a device layer including a plurality of circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects on a substrate; a memory device layer including a plurality of memory devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects; and contacts points coupled to one of ones of the first plurality of interconnects and ones of the second plurality of interconnects.