Monolithic 3D NAND Strings with Air Gaps for Capacitance Reduction

The fabrication process is segmented into distinct stages: forming sacrificial layers at specific depths, selectively removing portions of the substrate, and depositing insulating materials in between. This segmentation allows for precise control of the active region shape while simplifying each individual step, avoiding the need for repeated sidewall spacer formation and etching cycles.

Sacrificial layers are formed preliminarily at predetermined depths before the actual active region formation. These sacrificial layers guide the subsequent substrate removal process, ensuring that the active regions achieve the desired shape without requiring complex iterative adjustments during fabrication.

Multiple control gate electrodes are nested vertically above each other within a single memory cell structure. This nesting allows multiple bits of data to be stored in what would traditionally be a single-bit cell, thereby increasing storage density without proportionally increasing device complexity.

The patent transitions from a two-dimensional planar cell structure to a three-dimensional vertical architecture with multiple control gates stacked above the active region. This dimensional change enables multiple bits per cell by utilizing the vertical dimension for additional storage capability.

Insulating material layers are introduced as intermediaries between adjacent control gate electrodes. These insulating layers act as mediators that reduce the electrical capacitance between control gates while maintaining their close physical proximity, thus preserving high device density without excessive energy loss.

The insulating material is selectively placed in specific locations between control gate electrodes, providing localized capacitance reduction where needed. This local quality approach allows control gates to remain closely spaced for high density while minimizing parasitic capacitance through targeted insulation.