Monolithic 3D NAND Strings with Air Gaps
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Solution Overview
Problem
Current three-dimensional NAND string technologies face challenges in achieving high density and efficient memory storage due to complex and time-consuming processes, such as the formation of conical active regions and limited bit storage per cell, which hinder the development of advanced memory devices.
Innovation Solution
The development of a monolithic three-dimensional NAND string structure featuring a semiconductor channel with perpendicular extensions, multiple control gate electrodes, insulating material layers, and air gaps or low-k dielectric materials between device levels, along with discrete charge storage regions and tunnel dielectrics, to enhance storage capacity and reduce capacitance between control gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional three-dimensional NAND string structures are used, then manufacturing processes become complex and time-consuming, but storage density and program speed are limited
Solution Approach 1:
The patent transitions from conventional planar or simple vertical NAND structures to a multi-level three-dimensional architecture where control gate electrodes are stacked at different heights (first device level, second device level, third device level). This vertical stacking in the third dimension enables higher storage density and improved program speed by providing multiple storage nodes per channel, while the systematic layer-by-layer fabrication process manages the complexity through standardized repetitive steps.
Solution Approach 2:
The fabrication process is segmented into distinct, standardized stages: forming insulating material layers with air gaps, depositing control gate electrodes at different levels, creating charge storage regions, and forming tunnel dielectrics. Each segment can be independently optimized and repeated, reducing overall process complexity while enabling complex multi-level structures that improve productivity.
2Object-generated harmful factors
If conventional insulating material layers are used between device levels, then capacitance between control gates is high, but manufacturing process is simpler
Solution Approach 1:
The patent introduces air gaps within the insulating material layers between device levels. Air, being a low-dielectric constant material, significantly reduces the capacitance between control gate electrodes at different levels compared to conventional solid insulating materials. This porous structure (solid insulator with air voids) maintains mechanical integrity while eliminating the harmful capacitive coupling that would slow down programming operations.
Solution Approach 2:
The patent changes the dielectric parameter of the insulating material by incorporating air gaps, which have a dielectric constant of approximately 1, compared to conventional insulating materials with dielectric constants of 3-10. This parameter change directly reduces the capacitance between control gates, improving program speed without requiring fundamentally different manufacturing processes.
3Quantity of substance
If monolithic three-dimensional NAND string structure with air gaps is implemented, then storage density and program speed improve, but fabrication process becomes more complex
Solution Approach 1:
The patent implements a nested structure where charge storage regions are formed within the channels, which are surrounded by tunnel dielectrics, which are in turn surrounded by blocking dielectrics, all organized within a multi-level control gate architecture with air gaps. This nested arrangement maximizes storage density by utilizing multiple concentric functional layers, while each nesting level follows standardized fabrication sequences that manage the overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves storage density and program speed by simplifying the fabrication process, reducing capacitance, and enabling more efficient memory storage, thus addressing the limitations of existing NAND string technologies.
Implementation Method 1
The third insulating material portion includes a material that has a dielectric constant that is lower than a dielectric constant of a material of the first insulating layer portion and a dielectric constant of a material of the second insulating layer portion
Implementation Method 2
A tunnel dielectric is located between the charge storage region and the semiconductor channel
Data Source
AI summary
A vertically repeating stack of a unit layer stack is formed over a substrate. The unit layer stack includes a sacrificial material layer, a lower silicon oxide material layer, a first silicon oxide material layer, and an upper silicon oxide material layer. A memory opening can be formed through the vertically repeating stack, and a layer stack including a blocking dielectric layer, a memory material layer, a tunneling dielectric, and a semiconductor channel can be formed in the memory opening. The sacrificial material layers are replaced with electrically conductive layers. The first silicon oxide material layer can be removed to form backside recesses. Optionally, portions of the memory material layer can be removed to from discrete charge storage regions. The backside recesses can be filled with a low-k dielectric material and/or can include cavities within a dielectric material to provide reduced coupling between electrically conductive layers.