Monolithic 3D NAND Strings with Copper Control Gates
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Solution Overview
Problem
Current methods for manufacturing three-dimensional vertical NAND strings face challenges in achieving high density and efficient scaling due to limitations in control gate fabrication processes, leading to defects and reduced memory cell density.
Innovation Solution
The method involves forming a stack of alternating insulating and sacrificial layers over a substrate, creating back side openings, and selectively removing sacrificial layers to form recesses, where clam-shaped blocking dielectrics and control gates are formed, allowing for the integration of multiple memory levels without intervening substrates, enabling vertical scaling and higher memory cell density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional control gate fabrication processes are used, then manufacturing simplicity is maintained, but memory cell density and scaling efficiency deteriorate
Solution Approach 1:
The control gate fabrication is divided into multiple stages: forming mandrels in back side recesses, depositing blocking dielectric, creating clam-shaped blocking dielectric regions, forming barrier layers, and depositing copper control gate layers. This segmentation allows precise control of gate dimensions and positioning to achieve high density while maintaining manufacturability through standardized process modules.
Solution Approach 2:
The patent transitions from planar control gate structures to three-dimensional clam-shaped blocking dielectric regions with copper gates extending vertically. This dimensional change enables increased memory cell density by utilizing vertical space efficiently while maintaining scalable fabrication processes.
2Area of stationary object
If vertical scaling is implemented to increase memory cell density, then area efficiency improves, but control gate fabrication difficulty increases
Solution Approach 1:
Mandrels are formed in back side recesses before depositing the blocking dielectric and control gate layers. This preliminary action establishes precise spatial references that guide subsequent fabrication steps, enabling vertical scaling while maintaining manufacturing ease through pre-positioned structural elements.
Solution Approach 2:
Clam-shaped blocking dielectric regions serve as intermediaries between the copper control gates and the underlying mandrels/insulating layers. These intermediate structures facilitate the complex vertical scaling by providing isolation, structural support, and precise positioning references that simplify the overall fabrication process.
3Productivity
If copper control gates are used instead of conventional materials, then programming speed and data retention improve, but manufacturing complexity increases
Solution Approach 1:
The patent changes the material parameter from conventional polysilicon or metal gates to copper, which provides superior electrical conductivity for faster programming. The associated complexity is managed by integrating copper deposition into existing semiconductor fabrication workflows using established barrier dielectric and deposition techniques.
Solution Approach 2:
The control gate structure uses a composite arrangement of copper control gate layers combined with clam-shaped blocking dielectric regions and barrier layers. This composite structure achieves the desired electrical performance for high-speed programming while managing manufacturing complexity through modular material integration.
Data Source
AI summary
A monolithic three dimensional NAND string includes a semiconductor channel, with at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, and a plurality of copper containing control gate electrodes extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. The NAND string also includes a blocking dielectric located over the plurality of control gates, a tunnel dielectric in contact with the semiconductor channel, and at least one charge storage region located between the blocking dielectric and the tunnel dielectric.