Monolithic 3D NAND Strings with Segmented Charge Storage
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Solution Overview
Problem
Current three-dimensional vertical NAND strings have limitations, including providing only one bit per cell and requiring a complex and time-consuming process for active region formation, resulting in a conical shape that is difficult to achieve.
Innovation Solution
A method for forming monolithic three-dimensional NAND strings involves creating a stack of alternating conductive or semiconductor control gate material and insulating material layers over a substrate, etching to form openings, and selectively etching to create recesses for discrete charge storage segments, tunnel dielectric, and semiconductor channels, allowing for multiple bits per cell and improved manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional vertical NAND string process is used, then one bit per cell is achieved, but memory density is limited
Solution Approach 1:
The charge storage function is segmented into multiple discrete charge storage segments along the vertical channel, allowing multiple bits to be stored in a single cell. Each segment can independently store charge representing different bit values, thereby increasing memory density without requiring additional cells.
Solution Approach 2:
The patent transitions from a conventional two-dimensional planar structure to a three-dimensional vertical structure with multiple charge storage segments stacked along the vertical dimension. This dimensional change enables multiple bits per cell by utilizing the vertical space within the channel rather than requiring lateral expansion.
2Manufacturing precision
If repeated sidewall spacer formation and etching is used to form active regions, then the process achieves the desired structure, but manufacturing time and complexity increase
Solution Approach 1:
The active regions are formed with the desired shape during the initial deposition and patterning steps before subsequent processing. The alternating layers of control gate material and insulating material are deposited and patterned in advance to define the final active region geometry, eliminating the need for repeated sidewall spacer formation and etching cycles.
Solution Approach 2:
The complex repeated sidewall spacer formation and etching steps are extracted and replaced with a simplified direct patterning approach. The patent removes the unnecessary intermediate steps while maintaining the desired conical or tapered active region shape through optimized deposition and single-step etching processes.
3Manufacturing precision
If conventional etching processes are used, then openings are formed in the stack, but the conical shape is difficult to achieve with high precision
Solution Approach 1:
The etching process parameters are optimized to achieve the desired conical or tapered opening shape. By adjusting etch rate, selectivity, and anisotropy parameters, the patent enables precise formation of tapered openings that define the active regions and charge storage segments without requiring complex multi-step processes.
Data Source
AI summary
Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.