Monolithic 3D NAND String Formation via Selective Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current three-dimensional vertical NAND strings have limitations, including providing only one bit per cell and requiring a complex and time-consuming process for active region formation, resulting in a conical shape that is difficult to achieve.
Innovation Solution
A method for forming a monolithic three-dimensional NAND string involves creating a stack of alternating conductive or semiconductor control gate material and insulating material layers over a substrate, etching to form openings, and selectively etching to create recesses for discrete charge storage segments, tunnel dielectric, and semiconductor channels, allowing for multiple bits per cell and improved manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If repeated formation of sidewall spacers and etching of substrate is used to form active regions, then conical active region shape is achieved, but the process becomes difficult and time consuming
Solution Approach 1:
The patent applies preliminary action by forming the tunnel dielectric layer and charge storage layer on the substrate before forming the control gate electrodes and blocking dielectric. This sequence allows the conical active region shape to be achieved naturally during the deposition process without requiring repeated sidewall spacer formation and etching steps, thereby simplifying the overall manufacturing process while maintaining the desired geometry.
2Quantity of substance
If traditional vertical NAND string structure is used, then one bit per cell is achieved, but memory density is limited
Solution Approach 1:
The patent implements another dimension by transitioning from a traditional single-column vertical NAND string to a multi-column structure where multiple active regions are arranged in parallel columns. This dimensional expansion allows multiple charge storage layers to be positioned at different lateral locations, enabling multi-bit storage capacity per cell and significantly increasing memory density without requiring additional vertical stacking height.
3Productivity
If simplified manufacturing process is used, then manufacturing time is reduced, but manufacturing precision may be compromised
Solution Approach 1:
The patent uses the substrate as an intermediary platform that pre-defines the geometric framework for active region formation. By depositing the tunnel dielectric and charge storage layers conformally on the substrate surface, the substrate acts as a template that automatically ensures uniform thickness and precise positioning, eliminating the need for complex spacer-based patterning while maintaining high manufacturing precision.
Data Source
AI summary
A method of making a monolithic three dimensional NAND string is provided. A stack of alternating layers of a first material and a second material different from the first material is formed over a substrate. The stack is etched to form at least one opening in the stack. A charge storage material layer is formed on a sidewall of the at least one opening. A tunnel dielectric layer is formed on the charge storage material layer in the at least one opening. A semiconductor channel material is formed on the tunnel dielectric layer in the at least one opening. The first material layers are selectively removed to expose side wall of the charge storage material layer. A blocking dielectric is formed on the exposed side wall of the charge storage material layer. Control gates are formed on the blocking dielectric.