Monolithic 3D NAND Strings for High-Density Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current three-dimensional vertical NAND strings have limitations, such as providing only one bit per cell and requiring complex and time-consuming processes for active region formation, which complicates the manufacturing of high-density memory devices.
Innovation Solution
A method for creating monolithic three-dimensional NAND strings involves forming alternating layers of conductive or semiconductor control gate material and insulating material, etching to create recesses, forming blocking dielectric and discrete charge storage segments, and constructing semiconductor channels with tunnel dielectrics to enhance memory density and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional vertical NAND string processes are used, then manufacturing is simpler, but memory density is lower
Solution Approach 1:
The patent segments the continuous charge storage region into multiple discrete charge storage segments along the vertical channel. This segmentation enables multiple bits to be stored per cell by independently controlling each segment, thereby increasing memory density without requiring a complete redesign of the vertical NAND structure
Solution Approach 2:
The patent introduces an additional vertical dimension to the traditional two-dimensional memory cell layout by stacking multiple control gates and charge storage segments vertically. This three-dimensional configuration allows multiple bits to be stored in a single vertical column, significantly increasing memory density while maintaining a relatively simple planar process flow
2Manufacturing precision
If repeated sidewall spacer formation and etching are used, then active regions are formed, but manufacturing time increases
Solution Approach 1:
The patent performs preliminary patterning of the charge storage segments using mandrel structures and spacer formation before final active region definition. This preliminary action establishes precise vertical positions for charge storage segments, enabling subsequent steps to proceed more quickly without compromising precision
Solution Approach 2:
The patent introduces mandrel structures and spacer materials as intermediary elements to define the positions of charge storage segments. These intermediaries simplify the patterning process by providing temporary structures that guide material deposition and etching, reducing the number of direct lithography and etching cycles required
3Quantity of substance
If conventional NAND string structures are used, then one bit per cell is achieved, but memory capacity is limited
Solution Approach 1:
The patent implements a nested structure where multiple charge storage segments are positioned along the vertical channel, each associated with its own control gate. This nested arrangement of storage elements within a single vertical cell column enables multi-bit storage per cell, dramatically increasing memory capacity while maintaining a compact footprint
Data Source
AI summary
Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.