Monolithic 3D IC Placement Optimizing Inter-Layer Connectivity
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Solution Overview
Problem
Current CAD tools face challenges in optimizing the design of monolithic three-dimensional integrated circuits, particularly in minimizing the number of Through-Silicon Vias (TSVs) and leveraging dense inter-layer connectivity to enhance object placement and proximity in 3D space, which is not effectively addressed by traditional two-dimensional design methodologies.
Innovation Solution
The development of CAD tools that utilize a 2D placer and router to perform placement and routing across multiple strata in a monolithic 3D manufacturing process, optimizing partitioning and placement based on disparate characteristics of each layer, such as lithography requirements, power dissipation, and semiconductor materials, to maximize connectivity and reduce manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional two-dimensional design methodologies are used, then the design process is simpler, but the number of Through-Silicon Vias (TSVs) increases and inter-layer connectivity is not optimized
Solution Approach 1:
The patent transitions from traditional 2D placement methodologies to 3D placement across multiple strata. The system divides the design into multiple strata (first strata, second strata, etc.) and performs placement operations in three dimensions, allowing objects to be positioned vertically across different layers. This dimensional expansion reduces the need for TSVs by enabling direct 3D routing and optimizing inter-layer connectivity through strategic object positioning in the vertical dimension.
Solution Approach 2:
The patent segments the integrated circuit design into multiple discrete strata or layers. Each stratum can be independently processed and optimized, with objects placed on specific strata based on their characteristics and connectivity requirements. This segmentation allows the placement tool to manage complexity by handling one stratum at a time while achieving global optimization across all strata, thereby reducing overall TSV count through coordinated 3D arrangement.
2Quantity of substance
If monolithic 3D manufacturing process is implemented, then inter-layer connectivity is enhanced and TSVs are reduced, but the design process becomes more complex
Solution Approach 1:
The patent performs preliminary partitioning of the design into multiple strata before the actual placement process. The system identifies object characteristics, determines appropriate strata assignments, and prepares placement data structures in advance. This preliminary organization of design elements across strata simplifies the subsequent 3D placement operation by pre-establishing the vertical hierarchy and connectivity requirements, making the complex 3D process more manageable while achieving reduced TSV counts.
3Ease of manufacture
If objects are placed with optimal proximity in 3D space, then manufacturing cost is reduced, but placement optimization becomes more difficult
Solution Approach 1:
The patent applies different placement strategies and optimization criteria to different strata and object types based on their local characteristics. The system considers disparate characteristics of each layer (such as lithography requirements, power dissipation, and material properties) and optimizes placement locally for each stratum while maintaining global connectivity objectives. This localized optimization approach reduces manufacturing cost by placing objects with optimal proximity where appropriate, without requiring uniformly complex optimization across the entire design.
Data Source
AI summary
A method of designing 3D Integrated Circuits including: partitioning at least one design into at least two levels, a first and second level, where the first level includes logic, the second level includes memory; and then receiving a first placement of at least portion of the second level, where the first placement includes a placement of a first memory array, where the Circuit includes a plurality of connections between the first level and second level; performing a second placement of the first level based on the first placement, the performing a second placement includes using a placer computer executed, where the placer is a part of a Computer Aided Design tool, where the logic includes a first logic circuit configured to write data to the first memory array, and where performing the second placement includes placing the first logic circuit based on the first placement of the first memory array.