Monolithic 3D IC Placement Optimizing TSV Reduction
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Solution Overview
Problem
Current CAD tools face challenges in optimizing the design of monolithic three-dimensional integrated circuits, particularly in minimizing the number of Through-Silicon Vias (TSVs) and leveraging dense inter-layer connectivity to improve object placement and proximity in 3D space, which is not effectively addressed in traditional 2D CAD tools.
Innovation Solution
The solution involves extending CAD tool functionality to operate with a monolithic 3D manufacturing process, using 2D placers and routers to optimize the placement and routing of multiple layers of transistors and wires, focusing on leveraging dense inter-layer connectivity and disparate characteristics of layers to enhance physical proximity and reduce manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional 2D CAD tools are used for 3D IC design, then the design process can be maintained with existing tools, but the tools cannot effectively optimize placement and routing to minimize TSVs and leverage dense inter-layer connectivity
Solution Approach 1:
The patent extends traditional 2D CAD tools to operate in 3D space by introducing a vertical dimension (stacking layers). The system places objects on multiple strata (layers) and routes connections through 3D space, transforming 2D placement and routing algorithms into 3D-capable tools that can optimize monolithic 3D IC designs.
2Reliability
If Through-Silicon Vias (TSVs) are used for inter-layer connections, then layer connectivity can be achieved, but the number of TSVs increases manufacturing cost and complexity
Solution Approach 1:
The patent changes the connectivity parameter from sparse TSV-based connections to dense direct inter-layer connections enabled by monolithic 3D stacking. By altering the fundamental connection mechanism and leveraging the inherent dense connectivity of monolithic stacking, the system reduces reliance on TSVs while improving inter-layer communication efficiency.
3Area of stationary object
If object placement optimizes for 2D area utilization, then floorplan efficiency is improved, but 3D proximity and inter-layer connectivity are not optimized
Solution Approach 1:
The patent transitions from 2D area-optimized placement to 3D proximity-optimized placement by considering vertical stacking. Objects are placed on different strata to minimize 3D distances, and the placement algorithm optimizes for both 2D floorplan efficiency and 3D physical proximity, enabling better inter-layer connectivity without sacrificing area utilization.
Data Source
AI summary
A method of designing a 3D Integrated Circuit, the method including: performing partitioning to at least a logic strata, the logic strata including logic, and to a memory strata, the memory strata including memory; then performing a first placement of the memory strata using a 2D placer executed by a computer, where the 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices, where the 3D Integrated Circuit includes through silicon vias for connection between the logic strata and the memory strata; and performing a second placement of the logic strata based on the first placement, where the memory includes a first memory array, where the logic includes a first logic circuit controlling the first memory array, where the first placement includes placement of the first memory array, and the second placement includes placement of the first logic circuit based on the placement of the first memory array.