Monolithic 3D IC Placement via TSV Optimization
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Solution Overview
Problem
Current CAD tools face challenges in optimizing the design of monolithic three-dimensional integrated circuits, particularly in minimizing the number of Through-Silicon Vias (TSVs) and leveraging dense inter-layer connectivity to improve object placement and proximity in 3D space, which is not effectively addressed by traditional 2D CAD tools.
Innovation Solution
The solution involves optimizing CAD tools for monolithic 3D technology by using 2D placers and partitioners to strategically place and route objects across multiple strata, considering disparate characteristics such as lithography requirements, power dissipation, and manufacturing costs, and leveraging the rich vertical connectivity of monolithic 3D processes to optimize placement and routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional 2D CAD tools are used for monolithic 3D design, then the design process can be maintained with existing tools, but the ability to optimize TSV placement and leverage dense inter-layer connectivity is insufficient
Solution Approach 1:
The patent extends traditional 2D CAD tool functionality to operate with monolithic three-dimensional (3D) manufacturing process by introducing 3D spatial coordinates and inter-layer connection optimization, transforming the design space from two-dimensional to three-dimensional to leverage dense inter-layer connectivity
Solution Approach 2:
The patent modifies existing CAD tools to handle both traditional 2D IC design and monolithic 3D IC design, making the tools multi-functional by integrating 3D placement algorithms, TSV optimization, and inter-layer connectivity leverage while maintaining compatibility with existing design flows
2Reliability
If Through-Silicon Vias (TSVs) are used for inter-layer connections, then layer connectivity is achieved, but the size and cost of TSVs increase relative to lithography feature size
Solution Approach 1:
The patent optimizes TSV placement and sizing parameters by leveraging the regularity of monolithic 3D stacking, where TSV positions are determined by algorithmic placement rather than manual design, allowing systematic optimization of TSV diameter, spacing, and depth to reduce manufacturing complexity while maintaining connection reliability
3Productivity
If objects are placed to leverage dense inter-layer connectivity, then routing efficiency improves, but placement complexity increases compared to traditional 2D placement
Solution Approach 1:
The patent segments the placement problem into hierarchical levels: first determining optimal TSV locations and inter-layer connection points, then placing objects within each layer considering the fixed 3D connectivity structure, which breaks down the complex 3D placement into manageable stages and improves routing efficiency
Solution Approach 2:
The patent performs preliminary TSV placement and inter-layer connection determination before final object placement, establishing the 3D connectivity framework in advance to guide subsequent placement decisions and simplify the overall placement complexity
Data Source
AI summary
A method of designing a 3D Integrated Circuit, the method comprising: performing partitioning to at least a logic strata comprising logic and a memory strata comprising memory; then performing a first placement of said logic strata using a 2D placer executed by a computer, wherein said 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices, wherein said 3D Integrated Circuit comprises through silicon vias for connection between said logic strata and said memory strata; and performing a second placement of said memory strata based on said first placement, wherein said memory comprises a first memory array, wherein said logic comprises a first logic circuit controlling said first memory array, wherein said first placement comprises placement of said first logic circuit, and wherein said second placement comprises placement of said first memory array based on said placement of said first logic circuit.