Monolithic 3D IC Design via 2D Placer Partitioning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current CAD tools face challenges in efficiently designing monolithic three-dimensional integrated circuits due to the limitations of Through-Silicon Vias (TSVs) in stacked-layer processes, as they are large and expensive, whereas monolithic 3D processes require denser inter-layer connectivity and optimal placement of objects across layers with disparate characteristics.
Innovation Solution
The development of CAD tool methodologies that leverage dense inter-layer connectivity in monolithic 3D technology by using 2D placers for strata-specific placement and routing, partitioning based on disparate technology characteristics, and optimizing the placement of logic and memory layers to minimize expensive lithography processes and maximize connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If Through-Silicon Vias (TSVs) are used for inter-layer connection in stacked-layer processes, then layer connectivity is achieved, but the connection size becomes very large and expensive
Solution Approach 1:
The patent transitions from traditional 2D planar interconnection to 3D vertical stacking, enabling inter-layer connections through the third dimension. This allows multiple logic layers to be stacked vertically with interconnects formed between adjacent layers, reducing the need for large TSVs that penetrate entire wafer thicknesses.
Solution Approach 2:
The patent divides the monolithic structure into multiple active logic layers separated by thinner interconnect layers. This segmentation allows interconnections to be formed locally between adjacent layers rather than requiring long-distance TSVs, reducing connection size and cost while maintaining manufacturability.
2Productivity
If monolithic 3D process is used to achieve dense inter-layer connectivity, then connectivity density increases, but placement optimization across layers with disparate characteristics becomes more complex
Solution Approach 1:
The patent segments the monolithic 3D structure into distinct logic layers and interconnect layers, each with optimized characteristics. This allows independent optimization of each layer's placement and routing while maintaining overall system performance, reducing the complexity of global placement optimization across heterogeneous layers.
Solution Approach 2:
The patent applies different design rules, material compositions, and geometric parameters to different layers based on their specific functions. Logic layers have optimized transistor dimensions and spacing, while interconnect layers have optimized conductor width and spacing, allowing each layer to be placed and routed with locally optimized parameters rather than uniform global constraints.
Data Source
AI summary
A method of designing a 3D Integrated Circuit, the method including: performing partitioning to at least a logic strata including logic and a memory strata including memory; then performing a first placement of the logic strata using a 2D placer executed by a computer, where the 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices; where the 3D Integrated Circuit includes through silicon vias for connection between the logic strata and the memory strata; and performing a second placement of the memory strata based on the first placement, where the logic includes at least one decoder representation for the memory, where the at least one decoder representation has a virtual size with width of contacts for the through silicon vias, and where the performing a first placement includes using the decoder representation instead of an actual memory decoder.