Monolithic 3D Semiconductor Integration via Low-Temperature Oxide Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for constructing RGB LEDs, image sensors, displays, and solar cells face challenges such as high costs, inefficiencies, and thermal expansion coefficient mismatches, leading to issues like cracking and limited spectral capture, which hinder the development of more efficient and cost-effective devices.
Innovation Solution
The use of monolithic 3D integration techniques, including ion-cut, porous silicon approaches, and oxide-to-oxide bonding, allows for the construction of multi-level semiconductor devices with crystalline silicon and integrated circuits, enabling efficient layer transfer and bonding at temperatures below 400°C, thereby overcoming thermal expansion issues and improving device efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bonding methods are used to construct multi-level semiconductor devices, then device integration is achieved, but thermal expansion coefficient mismatches cause cracking and reliability issues
Solution Approach 1:
The patent introduces an intermediate oxide layer between dissimilar semiconductor substrates with different thermal expansion coefficients. This oxide layer acts as a stress-absorbing intermediary that accommodates thermal expansion mismatches during temperature cycling, preventing crack formation at the bonding interface while maintaining electrical and mechanical connectivity between layers.
2Strength
If high-temperature processing is used for layer transfer and bonding, then strong bonds are formed, but thermal damage occurs to sensitive device components
Solution Approach 1:
The patent modifies the bonding interface properties by introducing oxide layers that enable low-temperature oxide-to-oxide bonding. This parameter change in bonding mechanism allows achieving sufficient bond strength at temperatures below 400°C, preventing thermal damage to sensitive photodetector and circuit components while maintaining reliable inter-layer connectivity.
3Ease of manufacture
If simple planar structures are used, then manufacturing is easier, but spectral capture efficiency is limited
Solution Approach 1:
The patent transitions from planar 2D structures to vertically stacked 3D architectures, stacking multiple functional layers (photodetectors, circuits, waveguides) in the vertical dimension. This dimensional change enables enhanced spectral capture efficiency by allowing different photodetector layers to capture different wavelengths simultaneously while maintaining manufacturing simplicity through sequential layer deposition and bonding processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of more efficient and cost-effective RGB LEDs, image sensors, and solar cells by reducing thermal stress and processing costs, while enhancing spectral capture and device performance.
Implementation Method 1
an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds
Implementation Method 2
The use of monolithic 3D integration techniques, including ion-cut, porous silicon approaches
Implementation Method 3
The use of monolithic 3D integration techniques, including ion-cut, porous silicon approaches
Implementation Method 4
enabling efficient layer transfer and bonding at temperatures below 400°C, thereby overcoming thermal expansion issues and improving device efficiency
Data Source
AI summary
A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the first level includes crystalline silicon, where the second level includes crystalline silicon; an oxide layer disposed between the first level and the second level; and a plurality of electromagnetic modulators, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.