Monolithic 3D Semiconductor Integration Architecture

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Solution Overview

Problem

The semiconductor industry faces challenges in scaling integrated circuits beyond single-digit nanometer nodes due to limitations in two-dimensional (2D) scaling, necessitating the development of three-dimensional (3D) semiconductor circuits where transistors are stacked to increase transistor density and overcome area-based limitations.

Innovation Solution

A true monolithic 3D integration approach is implemented, where multiple semiconductor devices are vertically stacked in a single continuous process flow, with a wiring tier interposed between device tiers to facilitate electrical connections, reducing manufacturing costs and improving density through self-aligned and fully-aligned vias, and allowing for efficient transistor-to-transistor and gate-to-gate wiring without the need for monolithic inter-layer via.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If 2D scaling is continued to increase transistor density, then more transistors can be integrated on the substrate, but scaling enters single digit nanometer nodes where greater challenges arise

Engineering Contradiction:

Improvetransistor densityVSAvoidfabrication difficulty at single digit nanometer nodes

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent transitions from two-dimensional (2D) planar scaling to three-dimensional (3D) vertical stacking of semiconductor devices. Multiple tiers of devices are stacked vertically with wiring tiers and interconnect structures enabling electrical connections between tiers, thereby increasing transistor density without further reducing lateral dimensions to single-digit nanometer nodes

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If 3D semiconductor circuits are implemented with stacked transistors, then transistor density increases beyond 2D limitations, but device complexity and manufacturing process complexity increase

Engineering Contradiction:

Improvetransistor densityVSAvoidstructural complexity of stacked devices and wiring

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The 3D integrated circuit is segmented into multiple functional tiers: first tier devices, wiring tier, and second tier devices. Each tier can be independently designed and optimized for specific functions (e.g., logic, memory, I/O). This segmentation manages complexity by organizing the 3D structure into modular functional blocks with standardized interconnect interfaces

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A wiring tier is introduced as an intermediary layer between the first and second tiers of semiconductor devices. This wiring tier contains conductive interconnect structures that facilitate electrical connections between devices in different tiers, enabling complex 3D functionality while maintaining manageable device structures through standardized connection interfaces

Inventive Principle:

Principle #24Intermediary (Mediator)

3Adaptability or versatility

If 3D integration is implemented, then area-based limitations are overcome and more functions can be integrated, but manufacturing process complexity increases

Engineering Contradiction:

Improveintegration of heterogeneous functional circuitsVSAvoidmanufacturing process complexity

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent employs universal manufacturing processes and standardized interconnect structures that can be applied across different tiers and device types. The same fabrication techniques used for 2D devices are extended to 3D stacking, enabling heterogeneous integration of logic, memory, and I/O circuits while maintaining manufacturing efficiency through process reuse and standardization

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11201148B2Architecture for monolithic 3D integration of semiconductor devices

Publication Date: 2021.12.14 TOKYO ELECTRON LTD

AI summary

A three-dimensional (3D) integrated circuit (IC) includes a substrate having a substrate surface, a power rail provided in the substrate, and a first tier of semiconductor devices provided in the substrate and positioned over the power rail along a thickness direction of the substrate. A wiring tier is provided in the substrate, and a second tier of semiconductor devices is provided in the substrate and positioned over the wiring tier along the thickness direction. The second tier of semiconductor devices is stacked on the first tier of semiconductor devices in the thickness direction such that the wiring tier is interposed between the first and second tiers of semiconductor devices. A first vertical interconnect structure extends downward from the wiring tier to the first tier of semiconductor devices to electrically connect the wiring tier to a device within the first tier of semiconductor devices. A second vertical interconnect structure extends upward from the wiring tier to the second tier of semiconductor devices to electrically connect the wiring tier to a device within the second tier of semiconductor devices.