Monolithic 3D Semiconductor Integration via Low-Temperature Wafer Bonding
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Solution Overview
Problem
The challenge in monolithic three-dimensional integration of semiconductor devices lies in the temperature mismatch between transistor construction, which requires high temperatures, and wiring levels, which are constructed at lower temperatures, damaging materials like copper or aluminum when exposed to higher temperatures, hindering efficient 3D integrated IC fabrication.
Innovation Solution
The method involves ion implantation for thermal cleavage and oxide bonding of semiconductor wafers at temperatures less than 450°C, allowing for the formation of nanowire transistors with sources and drains through in-situ doping during epitaxial growth at low temperatures, enabling the integration of transistors in multiple tiers without damaging the wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high temperature processing is used for transistor construction, then transistor performance is improved, but wiring materials are damaged
Solution Approach 1:
The invention segments the integrated circuit fabrication into separate tiers: a first tier with transistors formed at high temperatures, and a second tier with wiring formed at low temperatures. This segmentation allows each component to be processed at its optimal temperature without interfering with the other, resolving the contradiction between high-temperature transistor construction and low-temperature wiring integrity
Solution Approach 2:
The invention transitions from planar 2D integration to 3D vertical integration by stacking transistor and wiring tiers in different spatial dimensions. This allows high-temperature processed transistor tiers and low-temperature processed wiring tiers to coexist without thermal interference, as they occupy different vertical positions in the three-dimensional structure
2Speed
If transistors are arranged in three dimensions, then wire length is reduced and signal delay decreases, but fabrication complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming transistor tiers at high temperatures, bonding tiers together, and then forming wiring at low temperatures. This segmentation simplifies the overall fabrication complexity by breaking down the complex 3D integration process into manageable, temperature-specific steps that can be executed sequentially using existing manufacturing techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient packing and connecting transistors in three-dimensional circuits without increasing interconnect signal delay, reduces metal layer usage, and enhances integration density and yield, facilitating high-performance three-dimensional ICs with reduced defect density and testing costs.
Implementation Method 1
implanting ions into a first semiconductor wafer to facilitate thermal cleavage
Implementation Method 2
The first semiconductor wafer is heated to a temperature equal to or less than 450° C. to cause thermal cleavage
Implementation Method 3
The first semiconductor wafer is heated to a temperature equal to or less than 450° C. to cause thermal cleavage so as to leave a portion of the first semiconductor wafer oxide bonded to the second semiconductor wafer
Implementation Method 4
Sources and drains for a plurality of nanowire transistors in the portion of the first semiconductor wafer oxide bonded to the second semiconductor wafer are formed by doping in-situ during epitaxial growth at temperatures equal to or less than 450° C.
Data Source
AI summary
A three-dimensional integrated circuit comprising top tier nanowire transistors formed on a bottom tier of CMOS transistors, with inter-tier vias, intra-tier vias, and metal layers to connect together the various CMOS transistors and nanowire transistors. The top tier first begins as lightly doped regions on a first wafer, with an oxide layer formed over the regions. Hydrogen ion implantation forms a cleavage interface. The first wafer is flipped and oxide bonded to a second wafer having CMOS devices, and the cleavage interface is thermally activated so that a portion of the lightly doped regions remains bonded to the bottom tier. Nanowire transistors are formed in the top tier layer. The sources and drains for the top tier nanowire transistors are formed by in-situ doping during epitaxial growth. After oxide bonding, the remaining process steps are performed at low temperatures so as not to damage the metal interconnects.