Monolithic 3D SRAM Structure With Cross-Tier Gate Layout
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Solution Overview
Problem
The integration and performance of static random-access memory (SRAM) devices need to be improved to meet the demands of faster operation speeds and higher accuracy, particularly in communication with central processing units (CPUs).
Innovation Solution
A monolithic three-dimensional stack structure for SRAM devices is implemented, comprising multiple tiers of transistors with channel layers made of two-dimensional semiconductor materials, and interconnects that facilitate electrical connections between transistors across tiers, enhancing the integration and performance of SRAM devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are arranged in a planar configuration, then device layout is simple, but integration density and communication efficiency with CPU are insufficient
Solution Approach 1:
The patent transitions from planar 2D transistor arrangement to three-dimensional vertical stacking, where multiple tiers of transistors are stacked along the vertical direction. This dimensional change dramatically increases integration density by utilizing the third dimension (height) rather than only horizontal plane, allowing more transistors to be packed into a smaller footprint area while maintaining simple process fabrication.
2Productivity
If more transistors are integrated to improve communication efficiency with CPU, then device complexity increases
Solution Approach 1:
By stacking transistors vertically in multiple tiers instead of expanding horizontally, the patent increases the number of transistors integrated in the SRAM device without proportionally increasing the planar footprint. This vertical integration approach improves communication efficiency with CPU by providing more memory cells closer to the processing unit while controlling the horizontal complexity of the device layout.
Solution Approach 2:
The patent implements a nested structure where multiple tiers of transistors are stacked one above another, with each tier containing transistors that are vertically integrated. The tiers are interconnected through vertical connections, creating a compact nested arrangement that increases transistor count without linearly increasing device complexity, as shared structures and interconnects serve multiple tiers simultaneously.
3Productivity
If transistor size is reduced to increase integration, then manufacturing precision requirements increase
Solution Approach 1:
Instead of reducing transistor dimensions in the horizontal plane which demands higher manufacturing precision, the patent increases integration density by extending in the vertical dimension. The transistor sizes within each tier can remain relatively large while multiple tiers are stacked vertically, thereby achieving high integration density without pushing the limits of horizontal lithography precision and manufacturing control.
Data Source
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Figure 3A
AI summary
Provided are a static random-access memory (SRAM) device having a monolithic three-dimensional stack structure and an electronic apparatus including the SRAM device. The SRAM device includes a first tier including first and second transistors, a second tier stacked on the first tier and including third and fourth transistors, and a third tier stacked on the second tier and including fifth and sixth transistors. Each of the first to sixth transistors includes a channel layer including a two-dimensional semiconductor material. A gate of at least one of the fifth and sixth transistors is arranged to intersect a gate of at least one of the first to fourth transistors.