Monolithic Capacitive Sensor with Through-Substrate Vias
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Solution Overview
Problem
Existing capacitive sensors face challenges in easy mounting and narrow production tolerances, leading to instability and increased parasitic capacitance when electrodes are mounted externally.
Innovation Solution
A monolithically integrated semiconductor device with through-substrate vias and metallizations connects capacitor electrodes at the same level, incorporating a floating coupling electrode for enhanced capacitive coupling, and optional dielectric material for gas or humidity sensing, allowing for precise patterning and reduced parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If capacitor electrodes are mounted externally on separate chips, then device complexity is reduced, but parasitic capacitance increases and measurement precision deteriorates
Solution Approach 1:
The patent merges the capacitor electrodes directly with the semiconductor substrate, integrating them into the same chip as the integrated circuit. This eliminates the need for separate chips and external mounting, thereby reducing device complexity while simultaneously minimizing parasitic capacitance and improving measurement precision through direct integration.
Solution Approach 2:
The patent transitions from a planar electrode arrangement to a three-dimensional structure by forming capacitor electrodes at different depths within the semiconductor substrate using through-substrate vias. This vertical dimensionality allows direct connection to the integrated circuit while minimizing parasitic effects and eliminating the need for external chip mounting.
2Ease of manufacture
If capacitor electrodes are mounted externally, then ease of manufacture is improved, but stability deteriorates due to increased parasitic capacitance
Solution Approach 1:
The patent combines the capacitor electrodes, integrated circuit, and substrate into a single monolithic structure. This integration eliminates external mounting steps while improving stability by minimizing parasitic capacitance, thereby achieving both ease of manufacture and high reliability simultaneously.
Solution Approach 2:
The patent introduces through-substrate vias with metallizations as intermediary structures that directly connect the integrated circuit to the capacitor electrodes within the substrate. This intermediary connection eliminates the need for external mounting while maintaining stability by minimizing parasitic capacitance through direct internal pathways.
3Manufacturing precision
If through-substrate vias are used to connect electrodes, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent merges the formation of through-substrate vias with the standard integrated circuit manufacturing process. By integrating via formation, metallization, and electrode patterning into a unified fabrication sequence, the patent achieves high manufacturing precision while avoiding the additional complexity of separate assembly steps.
Solution Approach 2:
The patent performs preliminary actions by forming the through-substrate vias and metallizations during the substrate preparation phase, before the integrated circuit and capacitor electrodes are fully assembled. This preliminary structuring enables precise alignment and connection while simplifying subsequent manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables stable and accurate capacitive sensing with minimized parasitic capacitance, facilitating easy mounting and precise layout, suitable for various sensor applications like acceleration, humidity, and gas detection, while allowing for external connections via solder balls.
Implementation Method 1
through-substrate vias with metallizations, each of the metallizations electrically connecting one of the electric conductors with either the capacitor electrode or the further capacitor electrode
Implementation Method 2
Capacitive sensors comprise an arrangement of electrodes and capacitor dielectric with a variable capacitance correlated to a physical quantity that is to be measured
Implementation Method 3
capacitor electrode and at least one further capacitor electrode arranged at or above the back surface... dielectric material arranged between the capacitor electrode, the further capacitor electrode
Data Source
Figure 1~2
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Figure 5~6
AI summary
The semiconductor device comprises a substrate (1) of semiconductor material, at least one integrated component (2) in the substrate at or near a main surface (1'), a plurality of electric conductors (3) at or above the main surface, the integrated component being electrically connected with the electric conductors, a capacitor electrode (11) and at least one further capacitor electrode (12) arranged at or above the opposite back surface (1'') of the substrate, and through-substrate vias (8) with metallizations (9). Each of the metallizations (9) connects one of the electric conductors (3) with either the capacitor electrode (11) or the further capacitor electrode (12). At least one coupling electrode (15) is arranged in the vicinity of the capacitor electrode (11) and the further capacitor electrode (12).