Monolithic Chiplet Integration Beyond Reticle Size Limits
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Solution Overview
Problem
Current semiconductor manufacturing methods for monolithic integrated circuits face challenges in achieving cost-effective, high-yield integration due to process complexity, thermal limitations, and limited die-to-die interconnects, which restrict bandwidth and increase costs in 2.5D/3D packaging systems.
Innovation Solution
A novel process for monolithic integrated circuits that combines multiple chiplets on a single semiconductor substrate, exceeding the limitations of photo mask areas by using die-to-die connection patterns and conductive wires, allowing for large-scale integration beyond reticle limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple chiplets are integrated on a single semiconductor substrate to achieve large-scale integration beyond reticle limits, then integration scale and bandwidth are improved, but fabrication complexity and process difficulty increase
Solution Approach 1:
The patent divides the large-scale integrated circuit into multiple separate chiplets that are fabricated independently on a semiconductor substrate. Each chiplet can be manufactured using standard lithography processes within reticle limits, then interconnected through conductive wires to achieve overall integration beyond reticle capabilities. This segmentation resolves the contradiction by enabling large-scale integration without requiring complex single-step lithography processes.
Solution Approach 2:
The patent transitions from planar 2D integration constrained by reticle area to three-dimensional integration by stacking chiplets vertically and connecting them through conductive wires that extend between different layers. This dimensional transition allows the system to achieve effective integration area exceeding the physical reticle limits while using conventional fabrication processes for each layer.
2Ease of manufacture
If conventional lithography tools are used for fabrication, then manufacturing cost is reduced, but exposure area is limited by reticle size
Solution Approach 1:
The patent segments the overall circuit design into multiple chiplets, each fitting within the exposure area limits of conventional lithography tools. This allows standard reticle-based fabrication processes to be used for each chiplet independently, maintaining cost-effectiveness while achieving total integration area that exceeds single-reticle capabilities through the combination of multiple smaller fabricated units.
Solution Approach 2:
The patent introduces conductive wires as intermediary elements that connect separate chiplets fabricated by conventional lithography tools. These wires serve as the bridging mechanism that allows individual chiplets, each created within reticle area constraints, to function together as a unified large-scale integrated circuit, effectively extending the usable exposure area beyond physical reticle limits.
3Productivity
If 2.5D/3D packaging systems are used to achieve high integration, then bandwidth is improved, but assembly cost and process complexity increase
Solution Approach 1:
The patent merges the interconnection function into the fabrication process itself by forming conductive wires that directly connect chiplets on the substrate during manufacturing. This integration of interconnect formation with chiplet fabrication eliminates the need for separate, complex assembly processes required by traditional 2.5D/3D packaging systems, thereby achieving high bandwidth while reducing assembly cost and process complexity.
Solution Approach 2:
The patent performs preliminary actions by pre-forming conductive connection structures on the substrate before chiplet placement and bonding. This advance preparation of interconnection pathways simplifies subsequent assembly operations and reduces the complexity of the overall manufacturing process compared to systems that require complex post-fabrication interconnection steps.
Data Source
AI summary
A semiconductor monolithic IC includes a semiconductor substrate having a rectangular shape in plan view, multiple chiplets each comprising a circuit, wherein the multiple chiplets are disposed over the semiconductor substrate and are separated from each other by die-to-die spaces filled with a dielectric material, and a plurality of conductive connection patterns electrically connecting the multiple chiplets so that a combination of the circuit of the multiple chiplet function as one functional circuit. The chip region has a larger area than a maximum exposure area of a lithography apparatus used to fabricate the first and second circuits.