Monolithic CMOS-MEMS Integration via Direct Metal Deposition
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Solution Overview
Problem
Current MEMS device integration methods result in bulky, costly, and power-hungry systems due to hybrid fabrication approaches, with high noise floors from parasitic effects and large size, especially in the Z direction, which restricts the use of integrated multi-sensing platforms in consumer electronics and automotive industries.
Innovation Solution
Direct fabrication of MEMS structures on CMOS substrates with metal interconnects, allowing for monolithic integration, reduced parasitic effects, and lower temperature processing, enabling smaller form factors, lower costs, and improved signal-to-noise ratios through optimized mechanical structures and reduced wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If hybrid fabrication approach is used to integrate MEMS devices and CMOS substrate, then device functionality is achieved, but device size becomes large and cost increases
Solution Approach 1:
The patent merges MEMS device fabrication with CMOS substrate processing by directly fabricating MEMS structures on the CMOS substrate using the same deposition and processing steps, eliminating the need for separate hybrid assembly and reducing overall device size
2Adaptability or versatility
If hybrid fabrication approach is used to integrate MEMS devices and CMOS substrate, then device functionality is achieved, but manufacturing cost increases
Solution Approach 1:
The patent combines MEMS and CMOS processing into a single unified fabrication process that uses the same deposition chambers, materials, and processing steps for both device types, eliminating the need for separate assembly operations and reducing manufacturing cost
3Productivity
If multiple wafer bonding is used to achieve wafer scale integration, then integration is achieved, but device size in Z direction remains large
Solution Approach 1:
The patent merges MEMS and CMOS processing into a single unified fabrication process that uses the same deposition chambers, materials, and processing steps for both device types, eliminating the need for separate assembly operations and reducing manufacturing cost
4Reliability
If metallic routings span through wafer thickness, then electrical connection is achieved, but parasitic capacitance increases and noise floor rises
Solution Approach 1:
The patent extracts the problematic long metallic routings that span through wafer thickness by directly fabricating MEMS structures on the CMOS substrate, thereby eliminating the parasitic capacitances and noise associated with these extended interconnect paths
5Strength
If silicon is used for MEMS elements, then structural strength is achieved, but deposition temperature exceeds CMOS thermal budget
Solution Approach 1:
The patent changes the material parameter from silicon to metal materials such as copper, aluminum, or tungsten that can be deposited at temperatures below 450°C, maintaining structural strength while complying with CMOS thermal budget constraints
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in compact, low-power, and cost-effective multi-sensing platforms with enhanced performance by eliminating the need for wafer bonding and reducing parasitic noise, enabling the integration of multiple MEMS elements on a single die with improved sensitivity and reduced power consumption.
Implementation Method 1
The structural material, whose main material is selected from the group consisting of metals and metal alloys, can be deposited directly on the CMOS substrate interconnect layers
Implementation Method 2
The structural material, whose main material is selected from the group consisting of metals and metal alloys, can be deposited directly on the CMOS substrate interconnect layers
Data Source
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AI summary
An assembly of metallic MEMS structures directly fabricated on planarized CMOS substrates, containing the application-specific integrated circuit (ASIC), by direct deposition and subsequent microfabrication steps on the ASIC interconnect layers, with an integrated cap for packaging, is provided. The MEMS structures comprise at least one MEMS device element, with or without moveable parts anchored on the CMOS ASIC wafer with electrical contact provided via the metallic interconnects of the ASIC. The MEMS structures can also be made of metallic alloy, conductive oxides or a combination of a few. The integrated cap, which provides a sealed cavity, is accomplished through bonding pads defined in the post-processing of the CMOS substrate or is directly fabricated on the CMOS substrate.