Monolithic Copper Post Structure for Wafer-Level Chip Scale Package
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Solution Overview
Problem
Conventional wafer-level chip scale packaging (WLCSP) processes requiring three or four lithographic masks are costly due to photolithographic operations and photomask production, necessitating a more economical method for forming copper posts and redistribution lines.
Innovation Solution
A two-mask process using one-piece copper or copper-containing layers with a one-step copper plating and etch-back process to form post-passivation interconnect (PPI) lines and copper posts, eliminating the interface between the PPI line and the copper post, thereby reducing costs and enhancing robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional three-mask or four-mask photolithographic processes are used to form copper posts and redistribution lines, then manufacturing precision and reliability are maintained, but fabrication costs increase significantly due to multiple photomasks and photolithographic operations
Solution Approach 1:
The patent combines the formation of copper posts and redistribution lines into a single copper layer deposition step, eliminating the need for separate photolithographic processes for each feature. This merging of previously separate manufacturing steps into one unified process directly reduces the number of photomasks required from three or four to just one, thereby significantly lowering fabrication costs while maintaining the necessary structural precision
Solution Approach 2:
The single copper layer serves multiple functions simultaneously: it forms both the copper posts for robustness and the redistribution lines for electrical interconnects. This multi-functional approach allows one material layer to fulfill roles that previously required separate processing steps, reducing overall process complexity and material costs
2Productivity
If separate copper post and PPI line structures are formed through multiple photolithographic masks, then functional separation is achieved, but manufacturing cost and process time increase
Solution Approach 1:
The patent merges the formation of copper posts and PPI lines into a single simultaneous deposition process, where both features are created in one step from the same copper layer. This eliminates the sequential time required for multiple separate photolithographic operations, directly improving manufacturing efficiency and reducing total process time
Solution Approach 2:
The single copper layer is deposited with predetermined patterns that pre-establish both the copper post locations and PPI line routes in one action. This preliminary formation of all copper features simultaneously eliminates subsequent time-consuming steps for creating additional copper structures, thereby accelerating the overall manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The two-mask process lowers fabrication costs by approximately 25% compared to conventional methods, while providing robustness to Ball Grid Array (BGA) balls through the monolithic copper structure, which acts as both a power line and a stress buffer without additional processes.
Implementation Method 1
a copper-containing layer is deposited in the opening and over the first polymer insulating layer
Implementation Method 2
an exposed portion of the copper-containing layer is etched using the conductive bump as a mask
Data Source
AI summary
In a method for forming a packaging structure, a metal pad is formed on a semiconductor substrate, and a first polymer insulating layer is formed over the semiconductor substrate. An opening passing through the first polymer insulating layer is formed to expose a portion of the metal pad. A copper-containing material is deposited in the opening and over the first polymer insulating layer, thereby forming a copper-containing layer having a first thickness and a first width over the first polymer insulating layer. A conductive bump having a second width is formed over the copper-containing layer, in which the second width is smaller than the first width. An exposed portion of the copper-containing layer is etched using the conductive bump as a mask until the exposed portion is reduced to a second thickness, thereby forming a monolithic copper-containing structure.