Monolithic Die Layout Stretching for Denser SRAM and Logic
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Solution Overview
Problem
The scaling of SRAM and logic circuits in monolithic semiconductor dies is hindered by the increase in die size due to the complexity of interconnection layers and the parasitic junction structures, which leads to inefficiencies in chip design and performance.
Innovation Solution
The proposed solution involves an integrated scaling and stretching platform that optimizes the dimension of standard cells and SRAM cells within the limitations of the Scanner Maximum Field Area, allowing for a smaller die area without shrinking the minimum feature size. This is achieved through precise control of transistor dimensions, self-aligned interconnection structures, and the distribution of metal wires under the silicon substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If process scaling technology is used to reduce minimum feature size from 28 nm down to 3-5 nm, then integration density and performance are improved, but manufacturing complexity and R&D investment costs increase dramatically
Solution Approach 1:
The patent introduces a stretching factor that operates in a dimensional space separate from traditional feature size scaling. By applying stretch factors (Sx, Sy) to standard cell dimensions, the patent achieves area reduction through geometric transformation rather than aggressive feature size shrinkage, thereby avoiding the manufacturing complexity associated with sub-5nm processes while still improving integration density
Solution Approach 2:
The patent changes the parameters of standard cell dimensions (width W, height H) by applying stretch factors to create stretched standard cells. This parameter transformation allows the same logical function to be implemented with reduced area without requiring changes to the underlying manufacturing process node, thus improving density while maintaining manufacturing feasibility
2Quantity of substance
If minimum feature size is shrunk to increase storage density, then SRAM capacity is improved, but area per bit increases due to parasitic junction structures and interconnection complexity
Solution Approach 1:
Instead of continuing to shrink features in all dimensions which increases parasitic effects, the patent applies differential stretching factors to modify the aspect ratio of SRAM cells. This dimensional transformation reduces the area occupied by parasitic structures and interconnections while maintaining the functional dimensions, thereby decreasing area per bit while increasing overall storage density
Solution Approach 2:
The patent applies stretching selectively to different regions of the SRAM cell layout. By locally modifying the dimensions of specific components (such as extending word lines or bit lines in certain directions while compressing others), the patent optimizes the area utilization and reduces the impact of parasitic structures in critical regions
3Adaptability or versatility
If more interconnection layers are added to support higher density, then circuit functionality is improved, but die area increases due to layout complexity
Solution Approach 1:
The patent uses stretching transformations to reorganize the spatial arrangement of interconnection layers and standard cells. By applying stretch factors to the layout, the patent can pack more interconnection structures into the available area more efficiently, reducing the overall die area required to support complex multi-layer interconnection architectures
Data Source
AI summary
The present invention provides a single monolithic die comprising a first schematic circuit manufactured based on a first technology node. A die area of the single monolithic die is smaller than a die area of another monolithic die with a second schematic circuit made based on the first technology node, wherein the first schematic circuit is the same as the second schematic circuit, and the first schematic circuit is a SRAM circuit, a logic circuit, a combination of SRAM and logic circuit, or a major function block circuit.