Monolithic Die Layout for SRAM Scaling Without M1 Interconnect
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling of SRAM and logic circuits in monolithic semiconductor dies is hindered by the increasing complexity of interconnection layers and the parasitic junction structures, leading to a dramatic increase in die size as the minimum feature size decreases.
Innovation Solution
The implementation of an integrated scaling and stretching platform that allows for the direct connection of gate and diffusion areas to the M2 interconnection layer without the need for a transitional M1 layer, along with the use of miniaturized transistor structures and novel CMOS designs to reduce latch-up distances and improve interconnect efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional scaling methods are used to reduce SRAM and logic circuit size, then minimum feature size must be shrunk, but this leads to increased die size, metal wire interference, and parasitic junctions
Solution Approach 1:
The patent redistributes metal interconnection wires from the horizontal plane to the vertical dimension by routing them through trenches and via holes in the substrate. This allows signals to travel through the third dimension (depth) rather than competing for horizontal space, eliminating metal wire interference while maintaining compact circuit area.
Solution Approach 2:
The patent segments the substrate into multiple isolated regions using deep trenches that extend through the silicon. These trenches create electrically isolated islands where n+ and p+ regions are separated, preventing parasitic junction formation while allowing independent optimization of each circuit block.
2Area of moving object
If minimum feature size is shrunk to scale down circuits, then circuit area reduces, but manufacturing complexity and costs increase dramatically
Solution Approach 1:
The patent changes the geometric parameters of the substrate structure by introducing deep trenches with specific depth and width ratios. These structural parameter changes enable circuit scaling without requiring proportional scaling of all feature dimensions, thereby reducing manufacturing complexity while achieving area reduction.
3Area of moving object
If n+ and p+ regions are placed closer to reduce area, then die size reduces, but latch-up occurs due to parasitic junctions
Solution Approach 1:
The patent uses deep trenches to segment the substrate into isolated regions, physically separating n+ and p+ regions. This segmentation prevents the formation of parasitic bipolar junctions that cause latch-up, allowing regions to be placed closer together while maintaining reliability.
Solution Approach 2:
The trenches act as intermediary isolation structures between n+ and p+ regions. These substrate isolations serve as mediators that electrically separate the regions, preventing direct interaction that would create parasitic junctions and latch-up conditions.
Data Source
AI summary
The present invention provides a single monolithic the comprising a first schematic circuit manufactured based on a first technology node. A die area of the single monolithic die is smaller than a die area of another monolithic die with a second schematic circuit made based on the first technology node, wherein the first schematic circuit is the same as the second schematic circuit, and the first schematic circuit is a SRAM circuit, a logic circuit, a combination of SRAM and logic circuit, or a major function block circuit.