Monolithic Floating Gate Memory Cell for CMOS Logic Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional logic gate fabrication processes lack the capability to integrate non-volatile memory blocks with stacked gate structures, limiting the integration of non-volatile memory with logic function blocks in single integrated circuits.
Innovation Solution
A non-volatile memory cell design that includes a coupling device and select transistors formed in conductivity regions, with a monolithically formed floating gate, allowing for compatibility with generic CMOS processes and enabling efficient programming and erasing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional logic gate fabrication processes are used, then manufacturing simplicity is maintained, but the capability to integrate stacked gate structures for non-volatile memory is lost
Solution Approach 1:
The patent designs a memory cell that can be fabricated using standard CMOS logic gate fabrication processes, making the manufacturing process universal and multi-functional. The stacked gate structure (floating gate and control gate) is integrated into a cell that uses conventional transistors and fabrication steps, allowing the same process line to produce both logic gates and non-volatile memory without requiring separate specialized processes.
Solution Approach 2:
The memory cell is segmented into distinct functional regions: a floating gate for charge storage, a control gate for programming/erasing control, and select transistors for cell access. This segmentation allows each component to be formed using standard CMOS processes while collectively achieving non-volatile memory functionality with stacked gate structure integration.
2Adaptability or versatility
If stacked gate structures are integrated for non-volatile memory, then memory functionality is achieved, but fabrication process complexity increases
Solution Approach 1:
The stacked gate structure serves multiple functions: the floating gate stores charge for non-volatile memory retention, the control gate enables programming and erasing operations, and together they form a compact memory cell that can be integrated with logic blocks. This multi-functionality is achieved within a structure that uses conventional CMOS fabrication steps.
Solution Approach 2:
The patent merges the floating gate and control gate into a single vertical stack, combining charge storage and control functions in one structure. This merged stacked gate structure is then integrated with select transistors to form a complete memory cell, reducing the overall device complexity compared to separate structures while maintaining full memory functionality.
3Ease of manufacture
If conventional memory processes are used, then process compatibility is maintained, but integration with logic function blocks is limited
Solution Approach 1:
The memory cell design uses universal CMOS fabrication processes that are already established for logic gate manufacturing. By using the same process steps (transistor formation, gate stacking, doping) for both logic and memory, the patent enables seamless integration of non-volatile memory blocks with logic function blocks on the same semiconductor substrate, achieving high adaptability while maintaining process compatibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves efficient programming and erasing operations while maintaining compatibility with CMOS processes, requiring a small layout area and exhibiting good speed, endurance, and data retention without degrading the cycling window.
Implementation Method 1
a coupling device and a first select transistor. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to a first floating gate transistor and a second select transistor, and the first select transistor, the first floating gate transistor, and the second select transistor formed in a second conductivity region. An electrode of the coupling device and a gate of the first floating gate transistor are a monolithically formed floating gate
Data Source
AI summary
The non-volatile memory cell includes a coupling device and a first select transistor. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to a first floating gate transistor and a second select transistor, all formed in a second conductivity region. An electrode of the coupling device and a gate of the first floating gate transistor are a monolithically formed floating gate; wherein the first conductivity region and the second conductivity region are formed in a third conductivity region; wherein the first conductivity region, the second conductivity region, and the third conductivity region are wells.